..................................................................................................................... III TABLE OF CONTENTS ................................................................................................... V LIST OF TABLES ........................................................................................................... VII LIST OF FIGURES ...............

we design and simulate a five-port optical router, which is composed of twenty mach-zehnder-based switching elements and twelve waveguide crossings for use in integrated photonic interconnection networks. we simulated and analyzed the operation of the proposed optical router from the aspects of insertion loss, power budget, q-factor and the minimum bit error ratio by use of optisystem simulator...

It is attractive to reuse the on-chip functional interconnects as test access mechanism (TAM) in network-on-chip (NoC) system testing. However, in the methodology of NoCreuse as TAM, the influence factors in NoC testing significantly increased. To further reduce test time and show significant gains over other work, we propose XY-direction connected subgraph partition (XYCSP) approach to elimina...

Modern systems-on-chip (SoCs) today contain hundreds of cores, and this number is predicted to reach the thousands by the year 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global ...

increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. nocs have features such as scalability and high performance. nocs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made noc. due to increasing number of cores, the placement of the cores i...

Nowadays, faults and failures are increasing especially in complex systems such as Network-on-Chip (NoC) based Systems-on-a-Chip due to the increasing susceptibility and decreasing feature sizes. On the other hand, fault-tolerant routing algorithms have an evident effect on tolerating permanent faults and improving the reliability of a Network-on-Chip based system. This paper presents reliabili...