Elektronische Systeme sind angesichts der zunehmenden Anforderungen an ihre Energieeffizienz immer häufiger mit einem aktivem Power-Management (PM) ausgestattet. Hierbei werden Spannungen und Frequenzen skaliert oder inaktive Bereiche zeitweise von der Versorgungsspannung getrennt. Die Steuerung erfolgt zumeist softwareseitig, wobei die Komplexität aufgrund der stetig wachsenden Anzahl von Powe...

Virtual prototypes are simulators used in the consumer electronics industry. They enable the development of embedded software before the real, physical hardware is available, hence providing important gains in speed of development and time-to-market. Transaction-level Modeling (TLM) is a widely used technique for designing such virtual prototypes. Its main insight is that many micro-architectur...

BACKGROUND The purpose of this study was to assess the feasibility of transoral laser microsurgery (TLM) in treatment of pT3 laryngeal cancer. METHODS We conducted a retrospective case series study of 226 patients with pT3 glottic (n = 122; 54%) or supraglottic laryngeal carcinoma (n = 104; 46%). All patients were treated by TLM in combination with neck dissection (63%) and with postoperative...

Background Transoral laser microsurgery (TLM) for early to intermediate laryngeal squamous cell cancer (SCC) can be technically challenging when adequate exposure of the posterior laryngeal compartment is required due to the presence of the orotracheal tube. The goal of our study was to analyze the efficacy of high frequency jet ventilation (HFJV) in achieving appropriate laryngeal exposure and...

Time-to-market pressure and productivity gap force vendors and researchers to improve embedded system design methodology. Current used design method, Register Transfer Level (RTL), is no longer be adequate to comply with embedded system design necessity. It needs a new methodology for facing the lack of RTL. In this paper, a new methodology of hardware embedded system modeling process is design...

Genome-wide systematic screens in yeast have uncovered a large gene network (the telomere length maintenance network or TLM), encompassing more than 400 genes, which acts coordinatively to maintain telomere length. Identifying the genes was an important first stage; the next challenge is to decipher their mechanism of action and to organize then into functional groups or pathways. Here we prese...

In recent years, transaction level modeling (TLM) has enabled designers to simulate complex embedded systems and SoCs, orders of magnitude faster than simulation at the RTL. The increasing complexity of the systems on one hand, and availability of low cost parallel processing resources on the other hand have motivated the development of parallel simulation environments for TLMs. The existing si...

With increasing number of IP cores, parallel communication architectures including NoCs have emerged for many-core systems. To efficiently architect NoCs, early analysis of crucial run-time metrics such as throughput, latency and saturation time is required. This requires abstract modeling of NoCs. Modeling abstraction, and consequently the modeling granularity impacts the accuracy and speed of...

Today's systems on chip (SoCs) require a complex design and verification process. In early stages, high-level debugging of the SoC functionality is feasible TLM (Transaction-Level Modeling) descriptions. To ease such SoC's models, Assertion-Based Verification (ABV) enables runtime temporal properties. last RTL (Register Transfer Level) descriptions hardware blocks expose microarchitectural deta...

The emergence of data-intensive applications, such as Deep Neural Networks (DNN), exacerbates the well-known memory bottleneck in computer systems and demands early attention design flow. Electronic System-Level (ESL) using SystemC Transaction Level Modeling (TLM) enables effective performance estimation, space exploration, gradual refinement. However, contention is often only detectable after ...