In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput and simple routing algorithm even if basic network problems such as deadlock and livelock are considered. We develop a new packet definition to support different requirements in an MIMD message passing architecture and also verify its efficienc...

A novel mapping of the Fuzzy ART algorithm onto a neural network architecture is described. The architecture does not utilize bi-directional synapses, weight transport, or weight duplication, and requires one fewer layer of processing elements than the architecture originally proposed by Carpenter, Grossberg, & Rosen (1991a). In the new architecture, execution of the algorithm takes constant ti...

The paper introduces ontogenic Fuzzy-CID3 algorithm (F-CID3) which combines a neural network algorithm and fuzzy sets into a single hybrid algorithm which generates its own topology. Two new methods, one based on a concept of a neural fuzzy number tree, and a class separation method are introduced in the paper and utilized in the algorithm. The F-CID3 algorithm is an extension of an ontogenic C...

A new VLSI architecture for real-time pipeline FFT processor is proposed. A hardware oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique in the divide and conquer approach. Radix-22 algorithm has the same multiplicative complexity as radix-4 algorithm, but retains the butterfly structure of radix-2 algorithm. The single-path delay-feedback architecture...

A new VLSI architecture for realtime pipeline FFT processor is proposed. A hardware oriented radix-2’ algorithm is derived by integrating a twiddle factor decomposition technique in the divide and conquer approach. R a d i ~ 2 ~ algorithm has the same multiplicative complexity as radix-4 algorithm, but retains the butterfly structure of radix-2 algorithm. The single-path delay-feedback architec...

Advancement in computer architecture leads to parallelize the sequential algorithm to exploit the concurrency provided by multiple core on single chip. Sequential programs do not gain performance from multicore. For multicore architectures, OPENMP and MPI are application programming interfaces. They can be used for parallelization of codes. For shared memory architecture OPENMP is used, whereas...

This work introduces a modified Grid Based Fuzzy System architecture, which is especially suited for the problem of time series prediction. This new architecture overcomes the problem inherent to all grid-based fuzzy systems when dealing with high dimensional input data. This new architecture together with the proposed algorithm allows the possibility of incorporating a higher number of input v...