This report presents the results of comparing four different frequency estimation schemes in the presence of high dynamics at low carrier-to-noise ratios. The comparison is based on measured data from a hardware demonstration. The tested algorithms include a digital phase-locked loop, a cross-product automatic frequency tracking loop, an extended Kalman filter, and finally, an FFT-aided cross-p...

We discuss the phase structure and fluctuations of conserved charges in two flavor QCD. The importance of the density fluctuations to probe the existence of the critical end point is summarized. The role of these fluctuations to identify the first order phase transition in the presence of spinodal phase separation is also discussed.

In previous work, we have shown that second-order phase locked loop (PLL) with sinusoidal phase detector characteristics have a separatrix cycle for a certain value of closed loop gain. It was verified that bifurcation from a stable separatrix cycle is the mechanism responsible for breaking the limit cycle associated with the PLL’s out-of lock state and the loop pulls in (phase lock). The value...

High-speed links which employ source synchronous clocking architectures have the ability to track correlated jitter between clock and data channels up to high frequencies. However, system timing margins are degraded by channel skew between clock and data signals and high-frequency loss. This paper describes how these key channel effects impact the jitter performance and influence the clocking a...

The standards governing the grid connection of distributed power generation systems (DPGS) are becoming increasingly demanding due to the growing number of alternative energies being connected to the grid. Grid connection standards now place greater emphasis on the fault ride-through capabilities of the DPGS. In order to fulfill these standards, improvements must be made to the grid-side contro...

A 0.5–5 GHz wide-range multiphase delay-locked loop (MDLL) with a calibrated charge pump is presented. A multiperiod-locked technique is used to enhance the input frequency range of a MDLL and avoid the harmonic-locked problem. The charge pump current is also calibrated to reduce the static phase error. This MDLL has been fabricated in 0.13m CMOS process. The measured root-mean-square and peak-...

A fully integrated phase-locked loop (PLL) fabricated in a 0.24μm, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24μm CMOS technologies. Also it has very low peak-to-peak jitter less tha...