This paper proposes a low power single-ended successive approximation register (SAR) analog-to-digital converter (ADC) to replace the only analog active circuit, the comparator, with a digital circuit, which is an inverter-based comparator. The replacement helps possible design automation. The inverter threshold voltage variation impact is minimal because an SAR ADC has only one comparator, and...

While transmitting the data over communication channel, various problems such as communication error and mismatch arises. For reducing those errors, frequency selective I/Q imbalance using Direct Conversion transmitters can be implemented. I/Q imbalance compensation procedure has been derived and incoherent measurements are required for avoiding the need for time, frequency and phase synchroniz...

Conversion of analog signals into digital signals is one of the most important functionalities in modern signal processing systems. As the signal frequency increases beyond 10 GHz, the timing jitter from electronic clocks, currently limited at approximately 100 fs, compromises the achievable resolution of analog-to-digital converters (ADCs). Owing to their ultralow timing jitter, the use of opt...

Imperfections in analog-to-digital conversion (ADC) cannot be ignored when signal digitization requirements demand both wide dynamic range and high resolution, as is the case for Majorana Demonstrator 76Ge neutrinoless double beta decay search. Enabling experiment's high-resolution spectral analysis efficient pulse shape discrimination required careful measurement correction of ADC nonlinearite...

This letter proposes a dynamic-range (DR) self-compensation technique to compensate the 6-dB DR loss caused by utilization of 1-MSB mismatch error shaping (MES) in noise (NS) successive-approximation-register ADC. The is realized using an additional conversion reduce total input voltage analog domain, preventing overload effect process. A compensation output binary code digital domain also adde...

Title of dissertation: HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS FOR MODERN SATELLITE RECEIVERS: DESIGN VERIFICATION TEST AND SENSITIVITY ANALYSIS Seokjin Kim Doctor of Philosophy, 2008 Dissertation directed by: Dr. Martin Peckerar Department of Electrical and Computer Engineering Mixed-signal System-on-chip devices such as analog-to-digital converters (ADC) have become increasingly prevalent in ...

In the paper, two approaches to measurements of circuit functions of analog parts of mixed-signal systems controlled by microcontrollers are presented. They base on the utilization of internal resources of the microcontrollers. The first approach uses an analog to digital converter (ADC), an analog comparator and a timer. The second one uses only the ADC and the timer. The measurement procedure...

he ever-dropping cost of Very Large Scale Integrated (VLSI) circuits allows many analog functions to be done digitally. However, the real world still is, and will always continue to be, a fundamentally analog place. Thus, the analog signal of interest is translated into a format that a digital computer can utilize. This translation is the function of an Analog to Digital Converter (ADC). After ...

This brief analyzes the performance of a new type of analog-to-digital converters (ADCs) architecture. The approach contemplates stretching the analog signal in time prior to digitization. Its benefits include an increase in the effective sampling rate and the input bandwidth, and a reduction in the sampling-jitter noise of the digitizer. It builds on the recent demonstration of high-speed anal...

Digital wireless communication applications such as UWB and WPAN necessitate low-power high-speed ADCs to convert RF/IF signals into digital form for subsequent baseband processing. Considering latency and conversion speed, flash ADCs are often the most preferred option. Generally, flash ADCs suffer from high power consumption and large area overhead. On the contrary, SAR ADCs have low power di...