Micromechanical devices like accelerometers or rotation sensors form an increasing segment beneath the devices supplying the consumer market. A hybrid integration approach to build smart sensor clusters for the precise detection of movements in all spatial dimensions requires a large toolbox of interconnect technologies, each with its own constraints regarding the total process integration. Spe...

A 0.25μm CMOS serializer ASIC, designed using radiation tolerant layout practice, was exposed to proton beam at various flux levels and accumulated fluence over 1.9×10 protons/cm (100 Mrad (Si)). The ASIC survived this total ionizing dose (TID) with no degradation in function. Single event effect (SEE) cross-sections are also calculated.

With reconfigurable computing a novel computing paradigm has emerged in the last few years that promises to be a valuable alternative to the traditional approaches like processors and ASICs. This report discusses the novel computing approach of reconfigurable computing and outlines the state of affairs in research and industry. The various approaches and directions are classified and discussed....

P. H. Tan,1,* X. D. Luo,2,5 Z. Y. Xu,1 Y. Zhang,3,† A. Mascarenhas,3 H. P. Xin,4 C. W. Tu,4 and W. K. Ge5 1State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, People’s Republic of China 2Jiangsu Provincial Key Lab of ASIC Design, Nantong University, Nantong, 226007, People’s Republic of China 3National Renewable ...

We describe an algorithm for interface synthesis and optimization for embedded system components such as microprocessors, memory ASIC, and network subsystems. The algorithm accepts the timing characteristics of two chips as input, and generates a combinational interface circuitry to implement communication between them. The algorithm consists of two parts. In the first part, we determine the di...

The key design metric in emerging applications such as wireless sensor networks, is the energy dissipated per function rather than clock speed or silicon area. The author’s previous energyscalable FFT ASIC uses an off-the-shelf standard-cell logic library and memory only scaled down to 1V operation [1]. This paper describes a custom real-valued FFT processor that operates over a variety of oper...

The main problem in hardware/software co-design is how to design an embedded system that contains both hardware in the form of FPGAs or ASICs and a microprocessor for which software must be written. A critical decision that has a profound effect on overall system cost is how to partition the system into its hardware and software components. A mistake made in this decision, which must be correct...

Presented is a new 80 GOPS video-processing chip capable of performing video rate vision applications. These applications include real-time video stabilization, mosaicking, video fusion, motion-stereo and video enhancement. The new vision chip, codenamed Acadia, is the result of over 15 years of research and development by Sarnoff in the areas of multi-resolution pyramid-based vision processing...

Addressing SWaP Challenges in Military Platforms With 65-nm FPGAs and Structured ASICs Introduction Now more than ever, size, weight, and power (SWaP) must be managed and reduced across virtually all military and aerospace applications to improve operational efficiency and logistics, increase mission life, and reduce the total cost of system ownership. System upgrades are driving added function...

The Scamseek project, as commissioned by ASIC has the principal objective of building an industrially viable system that retrieves potential scam candidate documents from the Internet and classifies them as to their potential risk of containing an illegal investment proposal or advice. The project produced multiple classifiers for different types of data, and achieved higher than expected perfo...