Reconfigurable computing is a computer architecture which is intended to fill the gap between the hardware and the software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware. Most commonly and widely used high speed computing fabrics deployed in reconfigurable computing are field-programmable gate arrays (FPGAs). This pap...

On-chip implementationofmultiprocessor systemsneeds toplanarise the interconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor Systems on Chips (MPSoC) node processors are homogeneous, and MPSoC network topologies are regular. Therefore, traditional ASIC floorplanning methodologies that perform macro placement are not suitable for MPSoC de...

In the CMS central tracker, the LHC clock and the first level trigger decisions are distributed encoded as a single signal. This paper describes an ASIC for clock recovery and first level trigger decoding to be used in the tracker data acquisition and slow control systems. The IC was implemented in a 0.25 Pm CMOS technology using a rad-tolerant layout. It recovers the clock and trigger signals ...

This paper presents an overview of the macro design, architecture, and built-in self-test (BIST) implementation as part of the IBM thirdgeneration embedded dynamic random-access memory (DRAM) for the IBM Blue Logic 0.11m application-specific integrated circuit (ASIC) design system (CU-11). Issues associated with embedding DRAM in an ASIC design are identified and addressed, including fundamenta...

This paper presents a platform for the parallel operation of VLSI neural networks allowing to seamlessly map neural network topologies on distributed resources. The scalable approach provides fast isochronous communication channels transporting the neuron signals between single network modules. The network modules are printed circuit boards hosting a programmable logic with an embedded micropro...

The RD51 collaboration maintains a common infrastructure at CERN for its R & D activities, including two beam telescopes test campaigns. Recently, one of the has been equipped and commissioned with new multi-channel charge-sensitive front-end electronics based on ATLAS/BNL VMM3a ASIC Scalable Readout System (SRS). This allows to read out detectors high rates (up MHz regime) time resolutions ord...

In a VHDL-based design flow for application specific integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The VITAL Standard includes specialized routines for describing behavior and timing of ASIC cells and integrates backannotation via Standard Delay Format (SDF). One of the key issues of the VITAL initiative was to accelerate simulat...

Two advanced design methodologies for hardware acceleration of a standard digital image restoration algorithm are explored and compared. The first one is the custom-designed hardware approach, leading to an application-specific integrated circuit (ASIC) implementation. The second one consists of the configurable processor approach, yielding a mixed hardware/software implementation running on a ...

In this paper, we present our stereo vision ASIC and a real-time upper body pose detection algorithm. The developed an ASIC which can generate QVGA(320×240) 30fps stereo map mounted on embedded system. We also developed a real-time upper body pose detection algorithm which is executed in the embedded system. The developed hardware and detection algorithm can extract various human upper body pos...