The chances of detecting a malicious reliability attack induced by an offshore foundry are grim. hardware Trojans affecting circuit’s do not tend to alter the circuit layout. These often manifest as increased delay in certain parts circuit. faults easily escape during integrated circuits (IC) testing phase, hence difficult detect. If additional patterns detect generated test pattern generation ...

We address the problem of verifying a retimed circuit. After retiming, some latches in a sequential circuit are repositioned to reduce the clock cycle time and thus the behavior of the combinational portion is changed, Here, we present a novel approach to check the correctness of a retimed circuit according to the dejinition of 3-valued equivalence. This approach is based on our verijication fr...

This paper presents two algorithms for generating compact test sets for combinational and full scan circuits under the transition and CMOS stuck-open fault models; Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR). These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combin-ational circuits, called MinTest. The te...

Design-for-test (DFT) is essential to ensure that complex designs can be thoroughly tested. Testing demands continue to increase as designs grow in gate count and fabrication process technologies evolve. Fortunately, advances in DFT techniques have avoided major design requirements and restrictions for test. In fact, some approaches have reduced the impact of test on designs. Structured DFT tec...

On Compact Test Sets for Multiple Stuck-At Faults for Large Circuits p. 20 Identification of Feedback Bridging Faults with Oscillation p. 25 Delay Fault and Memory Test Defining SRAM Resistive Defects and Their Simulation Stimuli p. 33 Vector-Based Functional Fault Models for Delay Faults p. 41 Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers p. 47 March Tests for Word-Ori...

In this paper the authors present a hierarchical Automatic Test Pattern Generation (ATPG) system, which searches for a compact set of test patterns, in an otherwise large search-space. A Genetic Algorithm (GA) is employed by the system, and the search for test patterns is guided by dynamically evolving a global record table (GRT), which is the prime component for directing the search towards an...

It is known that the ISCAS85 circuit c6288 contains an exponential number of paths and more than 99% of the path delay faults are untestable. Most ATPG tools which can efficiently handle other circuits fail on c6288. In this paper the logic structure of c6288 is studied and the main features which cause false paths are revealed. A heuristic which significantly helps the path delay fault test ge...

This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently combines several testing and test data compression approaches to enable application of a huge amount of ATPG and Weighed Random-BIST (WR-BIST) patterns. Results obtained from the application of the H-DFT technique to ...

Any input vector that does not detect a fault is called an antitest for that fault Given two faults an in put vector that detects exactly one of those faults is an exclusive test A concurrent test for two faults must detect both faults The problems of gener ating these three types of tests involve detection of multiple faults We transform each of these problems into a single fault ATPG problem ...