Results for linear and wide-dynamic range compression were compared with a new 64-channel digital amplification strategy in three separate studies. The new strategy addresses the requirements of the hearing aid user with efficient computations on an openplatform digital signal processor (DSP). The new amplification strategy is not modeled on prior analog strategies like compression and linear a...

In this paper, we present an analysis for the noise due to finite word length effects for digital signal power processors using Welch’s power spectrum estimation technique to measure the power of Gaussian random signals over a frequency band of interest. The input of the digital signal processor contains a finite-length time interval in which the true Gaussian signal is contaminated by Gaussian...

We investigate the performance of the routines in LAPACK and the Successive Band Reduction (SBR) toolbox for the reduction of a dense matrix to tridiagonal form, a crucial preprocessing stage in the solution of the symmetric eigenvalue problem. The target architecture is a current general purpose multi-core processor, where parallelism is extracted using a tuned multi-threaded implementation of...

A compact dual-band dual-polarized antenna is proposed in this paper. The two pair dipoles with strong end coupling are used for the lower frequency band, and cross-placed patch dipoles are used for the upper frequency band. The ends of the dipoles for lower frequency band are bent to increase the coupling between adjacent dipoles, which can benefit the compactness and bandwidth of the antenna....

Efficient decoding of Dual Tone Multi-Frequency (DTMF) signals can be achieved using the sub-band non-uniform discrete Fourier transform (SB-NDFT). In this paper, the details of its implementation on the ADSP-2192 processor are put forward. The decoder performance in terms of its computational complexity and computational speed of this algorithm, implemented on the ADSP-2192 processor, are comp...

We argue that currently developed software frameworks for active and programmable networking do not provide a truly generic approach to the development, deployment, and management of services. Furthermore, current systems are typically targeted at a particular level of the programmable networking design space (e.g. at low-level, in-band, packet forwarding; or at high-level signaling) and/or at ...

This paper describes a low-cost SDR implementation and performance evaluation of an IEEE 802.15.4 (ZigBee) baseband transceiver realized with a programmable Transport Trigger Architecture (TTA) Application Specific Processor (ASP). The SDR implementation has advantages over current System-on-Chip (SOC) implementations in terms of programmability and flexibility. The transceiver is designed for ...

The Alewife multiprocessor project focuses on the architecture and design of a large-scale parallel machine. The machine uses a low dimension direct interconnection network to provide scalable communication band-width, while allowing the exploitation of locality. Despite its distributed memory architecture, Alewife allows eecient shared memory programming through a multilayered approach to loca...

In this paper, we propose the parallel architecture for high speed calculations of SHA-1, a widely used cryptographic hash function. Parallel SHA-1 consists of a number of base modules which process the message digest in parallel manner. The base module uses state of art SHA-1 acceleration techniques: loop unfolding, pre-processing, and pipelining. We achieved the performance improvement of 5.8...

\ OX is a Natural Language Processor whose knowledge ran be extended by interaction with a user about these objects. The VOX analyzer uses information obtained in extensibility sessions to analyze novel text. 1.1 EXAMPLES VOX consists of a text analyzer and an extensibility system that share a knowledge base The extensibility system lets the user add vocabulary, concepts, phrases, events, and s...