Accurate instruction fetch and branch prediction is increasingly important on today’s superscalar architectures. Fetch prediction is the process of determining the next instruction to request from the memory subsystem. Branch prediction is the process of predicting the likely out-come of branch instructions. A branch target buffer (BTB) is often used to provide target addresses for taken branch...

The branch predictor plays a crucial role in the achievement of effective performance in microprocessors with pipelined architectures. This paper analyzes performance of branch prediction unit for pipelined processors. A memory of 512 bytes is designed for storing instructions. A 32 byte memory is designed for branch target buffer (BTB). This memory is utilized for storing history of the branch...

Energy-efficient dynamic branch predictors are proposed for the Cell SPE, which normally depends on compiler-inserted hint instructions to predict branches. All designed schemes use a Branch Target Buffer (BTB) to store the branch target address and the prediction, which is computed using a bimodal counter. One prediction scheme predecodes instructions when they are fetched from the local store...

Data collected from four distinct canopy positions from each of 39 Abies balsamea (L.) Miller trees were used to construct models to describe the cumulative leaf area distribution within the crown and to predict the needle mass of individual branches, the average branch angle, branch diameter, branch length, and crown radius per whorl, and the average number of living branches per whorl. We tes...

Indirect branch prediction is likely to become more important in the future because indirect branches tend to be more frequent in object-oriented programs. With indirect branch prediction misprediction rates of around 25% on current processors, such branches can incur a significant fraction of branch misses even though indirect branches are less frequent than the more predictable conditional br...

Most of the prediction mechanisms predict a single path to continue the execution on a branch. Alternatively, we may exploit parallelism from either possible paths of a branch, discarding wrong paths once the branch is resolved. This paper proposes a concept of Adaptive Branch Trees (ABT) to support highly speculative execution for processors with deeper pipelines and wide issue widths. The bas...

Conditional branches limit the speed of modern microprocessors. Researchers need tools to examine program branch behavior. HALT, the Harvard Atom-Like Tool, allows SUIF users to instrument conditional branch instructions in their programs. Instrumentation code enables research into the branch problem: how programs use conditional branches and how they can be handled efficiently during program e...

Efforts to reduce power consumption of processors have gained much attention recently. Dynamic branch predictor, including BTB, is exercised in every instruction cycle, yet branch instructions only constitute a small percentage of instructions during program execution. This study proposes a novel method to collect the next branch distances of the recent branch instructions at runtime, in order ...

We describe a new branch predictor that is designed to balance multiple constraints—predicting branch biases versus predicting specific branch instance behavior. Most branch instances only require branch bias information for accurate predictions while a select few require more sophisticated prediction structures. Our predictor uses a cache mechanism to classify branches and dynamically adjust t...

Intermittent left bundle branch block is uncommon. During anaesthesia,, left bundle branch block may be related to hypertension or tachycardia and its occurrence makes the diagnosis of acute myocardial ischaemia or infarction difficult. Patients with intermittent left bundle branch block often develop established left bundle branch block, which may represent an earlier state of ischaemic heart ...