Formerly, IC manufacturers applied DFT and BIST to increase yield and the reliability. However, how to balance redundancy utilization in an embedded memory core is still not known. Choi et al. proposed an approach to balance DFT and BIST. In this paper, some technical background is commented.

This paper compares the performance of linear and non-linear machines when they are used as the Pseudo Random Pattern Generators (PRPG) to detect faults in sequential circuits. Both transition test and fault simulation experiments are conducted. Results show that the non-linear machines have higher transition capability and exhibit better performance than the linear machine.

physical activity is connected with adults’ health in many ways, and walking is the most popular form of physical activity among adults all over the world. the authors have previously studied this issue in an under-construction environment in a new town in a developing country. the present study investigates the impact of built environmental features and qualities on walkability in developed ar...

Microprocessor design techniques have evolved to a point where large systems, such as S/390@ servers, can be constructed using relatively few, but very complex, applicationspecific integrated circuits (ASICs). Delivery of a quality design in a timely fashion requires that several design activities progress simultaneously, with different types of verification used within the various design disci...

Over the last 2-3 years, there has been a major change in the IC industry from being predominantly “functionalbased testing” to being predominantly “scan-based testing” (for new design starts). As recently as 2-3 years ago, the topic of panels was “Is scan-based testing feasible for all products?” The question has now changed to “Can we completely avoid functional testing?” I believe the same t...

A Low Transition LFSR(LT-LFSR) designed by modifying Linear Feedback Shift Register is proposed to produce low power test vectors which are given to Circuit under Test (CUT) to reduce the power consumption by CUT. This technique of generating low power test patterns is performed by increasing the co-relativity between the consecutive vectors by reducing the number of bit flips between successiv...

This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate efficient patterns to be used during BIST test pattern generation. The main idea is that test patterns detecting random pattern resistant faults are not embedded in a pseudo–random sequence as in existing techniques, but rat...

High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution. By proving the effectiveness ...

The System-On-Chip (SOC) revolution has brought some new challenges to both design and test engineers. The most important challenges of today’s VLSI systems testing are linked to test cost, defect coverage and power dissipation. Implementing a self-testable system may reduce test costs as expensive external high performance test equipment is not required and it may increase defect coverage as t...

In this paper, built-up land expansion patterns and the associated factors were characterized in urban and non-urban areas across the Wen-Tai region of eastern China. Fractal dimension can be used as a reliable indicator of the complexity of built-up land form, and the increasing trend of fractal dimension indicated a more complex, dispersed pattern of built-up land in urban areas. Spatial regr...