In this paper the first code-disjoint totally self-checking carry-select adder is proposed. The adder blocks are fast ripple adders with a single NAND-gate delay for carry-propagation per cell. In every adder block both the sum-bits and the corresponding inverted sum-bits are simultaneously implemented. The parity of the input operands is checked against the XOR-sum of the propagate signals. Fo...

With the continuing trends to reduce the chip size and integrates multichip solution into a single chip solution it is important to limit the silicon area required to implement parallel FIR digital filter in VLSI implementation. The Need for high performance and low power digital signal processing is getting increased. Finite Impulse Response (FIR) filters are one of the most widely used fundam...

In this paper, a novel technique for multiplication is presented using Vedic multiplier. Vedic multiplier uses adders and hence making fast adder will increase the overall speed for multiplication. We have done comparative analysis for multiplication using different architectures of adder. For comparison we have taken Carry Select Adder (CSA), Square Root Carry Select Adder (SQRT-CSA). We have ...

Arithmetic and Logic Unit (ALU), core unit of a processor, when used for scientific computations, will spend more time in multiplications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. Reducing delay in the multiplier reduces the overall computation time. Wallace multipliers perform in parallel, resulting in high speed. It uses...

We performed the measurement of the inclusive electron scattering off the proton [1, 2] in the resonance region (W < 2.5 GeV) at momentum transfer Q below 4.5 (GeV/c) with the CLAS detector. The large acceptance of CLAS provided an access to a large, continuous two-dimensional kinematic domain in Q and x, allowing therefore an integration of the data at fixed Q over x-interval. The covered x-in...

we proposed a new adder design, called VariableLatency Adder (VL-adder). This technique allows the adder to work at a lower supply voltage than that required by a conventional adder, while maintaining the same throughput. The VL-adder design can be further modified to overcome the effects of Negative Bias Temperature Instability (NBTI) on circuit delay. By applying VL-adder concept to 64-bit ca...

Although the majority of concept-learning systems previously designed usually assume that their training sets are well-balanced, this assumption is not necessarily correct. Indeed, there exist many domains for which one class is represented by a large number of examples while the other is represented by only a few. The purpose of this paper is 1) to demonstrate experimentally that, at least in ...