The synchronous microcontroller is a common processor found in many embedded system. By using asynchronous design techniques, the performance of the microcontroller is increased. Through the simulation and existing synchronous design tools in the asynchronous design flow, a “clock enabling technique” is simulated and then implemented. The asynchronous architecture includes an ALU, a decoder, a ...

This paper demonstrates two methods which simultaneously undertake synchronization and ranging based on a time-of-arrival approach with bidirectional communication to bypass the need for accurate synchronous clocking. In order to alleviate multipath effects, Tomlinson-Harashima precoding and UWB signaling are used to measure the distance between pairs of sensors. The proposed schemes are shown ...

A new static differential double edge-triggered flip-flop is proposed. In order to ensure the double edge triggering operation. a narrow pulse is generated after each clocking edge, by means of clock racing. Compared to existing double edge-triggered flipflops, the presented circuit configuration presents improved delay characteristics, reduced power consumption. while keeps the total transisto...

We propose an approach to quantum error correction based on coding and continuous syndrome readout via scattering of coherent probe fields, in which the usual steps of measurement and discrete restoration are replaced by direct physical processing of the probe beams and coherent feedback to the register qubits. Our approach is well matched to physical implementations that feature solid-state qu...

Synchronous clocking has continued to be the dominant digital design method despite the problems of clock distribution in integrated circuit chips of increasing complexity and speed. The continuing increases will soon force a change to asynchronous design methods, and the communication between large numbers of high-performance processors on a single chip will become a critical issue. An introdu...

The IBM POWER6e microprocessor is a high-frequency (.5-GHz) microprocessor fabricated in the IBM 65-nm silicon-oninsulator (SOI) complementary metal-oxide semiconductor (CMOS) process technology. This paper describes the circuit, physical design, clocking, timing, power, and hardware characterization challenges faced in the pursuit of this industryleading frequency. Traditional high-power, high...

In this paper a new dynamic differential logic style is presented. A non-precharged single phase clocking scheme is used. The logic is suitable for high speed and low power operation in both bit-serial and bit-parallel implementations, since all logic nets are purely in NMOS and merged with the latches. The logic style is also robust for clock slope and yield a data noise margin equal to Vdd/2.