This paper presents low power operation of barrel shifter and rotator which are designed and simulated in 2 phase clocked adiabatic static CMOS logic. The power consumption of the circuits is compared with that of static CMOS logic. A barrel logic right shifter, a right rotator and shift/rotator are simulated in 45nm CMOS process technology. A mux based design is used for all the above circuits...

We present Output Prediction Logic (OPL), a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the restoring character of the logic family, including its high noise margins. Speedups of 2X to 3 X over (optimized) conventional static CMOS are demonstrated for a variet), of circuits, ranging from chains of ga...

Versatile dual-mode class-AB CMOS four-quadrant analog multiplier circuit is presented. The dual translinear loops and current mirrors are the basic building blocks in realization scheme. This technique provides; wide dynamic range, wide-bandwidth response and low power consumption. The major advantages of this approach are; its has single ended inputs; since its input is dual translinear loop ...

The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in de...

IN CMOS TRANSLINEAR CIRCUITS Reid R. Harrison Computation and Neural Systems Program 139-74, California Institute of Technology, Pasadena, CA 91125 [email protected] ABSTRACT The exponential behavior of MOSFETs in subthreshold operation has recently been exploited to build CMOS translinear circuits such as multipliers and log-domain lters. A major obstacle in developing a practical CMOS...

In order to cope with the increasing leakage power and the increasing device variability in VLSI’s, the required control size of both the space-domain and the time-domain is decreasing. This paper shows the several recent fine-grain voltage engineerings for the low power VLSI circuit design. The space-domain fine-grain voltage engineering includes the fine-grain power supply voltage with 3D-str...

Principles and possibilities for design and implementation of parallel analog to digital converters for application in ternary CMOS digital systems are considered and proposed in the paper. Such converters perform signal conversion from analog to ternary digital signal in CMOS ternary digital systems. First, general principle and structure for implementation and design of CMOS parallel analog t...

Abstract On-chip electrostatic discharge (ESD) protection circuits had been built in IC chips to protect the devices and circuits against ESD damage. But, ESD protection circuits constructed with the scaled-down CMOS devices are very weak to ESD stress. Therefore, novel ESD protection solutions must be developed to overcome this reliability challenge for integrated circuits fabricated in the na...

The number of wireless communication links is witnessing tremendous growth and new standards are being introduced at high pace. These standards heavily rely on digital signal processing, making CMOS the first technology of choice. However, RF CMOS circuit development is costly and time consuming due to mask costs and design iterations. This pleads for a Software Defined Radio approach, in which...

The new emerging non-volatile memory (NVM) devices known as memristors could be the promising candidate for future digital architecture, owing to their nanoscale size and its ability integrate with existing CMOS technology. device has involved in various applications from design analog circuit design. In this paper, a combination of memristor transistors is working together form hybrid CMOS-mem...