A humidity microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm CMOS (complementary metal oxide semiconductor) process was presented. The integrated sensor chip consists of a humidity sensor and a readout circuit. The humidity sensor is composed of a sensitive film and interdigitated electrodes. The sensitive film is titanium dioxide prepared by the so...

We describe a hierarchical structure for a knowledge-based analog circuit synthesis tool. Analog circuit topologies are represented as a hierarchy of abstract functional blocks each with associated design knowledge. We also describe mechanisms to select from among alternate design styles, and to translate performance specifications from one level in the hierarchy to the next lower level. A prot...

A high-performance ASIC has been developed to serve as the interface for the 10-ns bus in the new AlphaServer 8000 series server systems from Digital. The CMOS standard-cell alternative (CSALT) technology provides a timing-driven layout methodology together with a correct-by-construction approach for managing the complex device physics issues associated with state-of-the-art CMOS processes. The...

Hybrid “CMOL” integrated circuits, incorporating advanced CMOS devices for neural cell bodies, nanowires as axons and dendrites, and singlemolecule latching switches as synapses, may be used for the hardware implementation of extremely dense (~10 cells and ~10 synapses per cm) neuromorphic networks, operating up to 10 times faster than their biological prototypes. We are exploring several “Cros...

In this thesis three novel analog techniques for testing CMOS Integrated circuits are presented. These techniques are based on analog circuits since they offer a number of important advantages compared to standard digital test techniques, such us less silicon area, lower power consumption and high operating speed. Therefore, the proposed techniques can be embedded in the circuit under test, con...

This paper describes an ASIC yield model based on the CMOS bridge fault model. The model predicts defect sensitive area early in the design cycle as a function of number of gates and nets.

To meet the desired electrostatic discharge (ESD) robustness, ESD diodes was added into the I/O cells of integrated circuits (ICs). However, the parasitic capacitance from the ESD diodes often caused degradation on circuit performance, especially in the high-speed I/O applications. In this work, two modified layout styles to effectively improve the figures of merits (FOMs) of ESD protection dio...

The main objective of this article is to describe the development of a fully-integrated disposable lab-on-achip for point of care testing and monitoring of biochemical parameters in biological fluids. The lab-on-achip is composed mainly by two dies: the fluid and the detection. The fluid die, fabricated in SU-8, comprises three microfluidic cuvettes, containing the fluids into analysis, and a β...