Since the invention of the integrated circuit technologies, there has been an unprecedented growth of the electronic industry, with significant impact on the maritime industry. In the last twenty years and so, the strongest growth area of the electronic industry has been in CMOS VLSI technology. The sustained growth in CMOS VLSI technology is fueled by a continued shrinking of transistors to ev...

This paper discusses the effects of MOSFET threshold voltage variations on the reliability of nanometer-scale CMOS logic gates. The reliability is quantified in terms of the probability-of-failure of individual CMOS gates, which is obtained from extensive Monte Carlo simulations of these gates. The study considers different nano-scale CMOS technology generations and compares the effect of thres...

This paper presents and discusses digital pixel readout integrated circuit architectures for long wavelength infrared (LWIR) in CMOS technology. Presented architectures are designed for scanning and staring arrays type detectors respectively. For scanning arrays, digital time delay integration (TDI) is implemented on 8 pixels with sampling rate up to 3 using CMOS 180nm technology. Input referre...

A SRAM cell must meet requirements for operation in submicron. As the density of SRAM increases, the leakage power has become a significant component in chip design. The power Consumption is a major issue of today's CMOS Technology. Leakage power is major issue for short channel devices. As the technology is shrinking the leakage current is increasing very fast. so, several methods and techniqu...

In this paper, the nano-CMOS hybrid Autonomous Error-Tolerant (AET) cellular network architecture, which integrates today’s mature CMOS technology with emerging nanotechnology, is proposed. Within the cellular network, each AET cell contains a nanocore, CMOS cell peripherals and their interface circuits. The overall network is homogenous. These imply strict constraints for intercellular connect...

Conventional asynchronous control circuit design is complex because potential designs must be analysed for the existence of hazards and state variable races, as these may cause incorrect circuit operation. We present the innovative CMOS direct-mapped asynchronous circuit design approach, which, by defining a one-to-one mapping between state diagram and CMOS circuit implementation, removes the n...

CMOS Integrated Circuit Design for Ultra-Wideband Transmitters and Receivers. (August 2009) Rui Xu, B.S. , Southeast University, China; M.S., Southeast University, China Chair of Advisory Committee: Dr. Cam Nguyen Ultra-wideband technology (UWB) has received tremendous attention since the FCC license release in 2002, which expedited the research and development of UWB technologies on consumer p...

Nanotechnology is derived from the evolution of microelectronics towards miniaturization. CMOS Technology has been targeted to integrate more and more Devices per unit area of Silicon-substrate, but there is limitation in scaling-down CMOS Circuits/Devices. Like Nanotechnology, QCA (Quantum-Dot Cellular Automata) is another alternate Technology having ability to reduce the Device-sizes beyond t...

Recent Technological advances in Wireless Communication has shown the convergence of terminals and networks that support multimedia and real-time applications. This obviously puts an immense pressure on battery of any mobile device. The CMOS has been the leading technology in today’s world of mobile communication due to its low power consumption. Reduction of leakage power in CMOS has been the ...

Abstract On-chip electrostatic discharge (ESD) protection circuits had been built in IC chips to protect the devices and circuits against ESD damage. But, ESD protection circuits constructed with the scaled-down CMOS devices are very weak to ESD stress. Therefore, novel ESD protection solutions must be developed to overcome this reliability challenge for integrated circuits fabricated in the na...