Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os. The trade-off between test application time, test bandwidth and area overhead should be exploited since it imposes certain restrictions on the Test Access Mechanism to be implemented. We outline an aliasing-free spac...

Embedded cores are being increasingly used in the designs of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model has been used for verifying core-based designs (Tung and Jou, 1998) . In this paper, we present an automatic-verification pattern ge...

In this paper we propose a procedure for determining 0– or 1– cover of an arbitrary line in a combinational circuit. When determining a cover we do not need Boolean expression for the line; only the circuit structure is used. Within the proposed procedure we use the tools of the cube theory, in particular, some operations defined on cubes. The procedure can be applied for determining 0– and 1– ...

In this short survey I mainly discuss some recent problems which occupied me and my colleagues and collaborators for the last few years . I will not give proofs but will either give references to the original papers or to the other survey papers . I hope I will be able to convince the reader that the subject is "alive and well" with many interesting, challenging and not hopeless problems . Deve...

Embedded cores are being increasingly used in large system-on-a-chip (SoC) designs. The high complexity of SoC designs lead the design verification to be a challenge for system integrators. This paper presents an automatic interconnection rectification (AIR) technique based on the port order fault model to detect, diagnose, and correct the misplacements of interconnection that occurred in the i...

This thesis presents two new methods of test-per-clock BIST design for combinational circuits. One of them is based on a transformation of the PRPG code words into test patterns generated by an ATPG tool. This transformation is done by a combinational circuit. For a design of such a circuit two major tasks have to be solved: first, the proper matching between the PRPG code words and the test pa...

In this paper, a new approach for generating test vectors that detects faults in combinational circuits is introduced. The approach is based on automatically designing a circuit which implements the -algorithm, an automatic test pattern generation (ATPG) algorithm, specialized for the combinational circuit. Our approach exploits fine-grain parallelism by performing the following in three clock ...

This paper shows that the kernel fragment of Esterel corresponding to combinational circuits admits a natural game–theoretic interpretation. Technically, combinational Esterel programs are mapped into finite two–player games in such a way that the standard must– and cannot–analysis of signal statuses is reflected in the computation of winning strategies. The novel game–theoretic approach comple...