We present a technique for redundancy elimination in multiplierless linear systems, such that the critical path of the computations is not increased. To the best of our knowledge this is the only method that combines common subexpression elimination and delay optimization in one single step. We assume that all the constant multiplications are decomposed into additions/subtractions and shift ope...

Meeting the tight performance specifications mandated by the customer is critical for contract manufactured ASICs. To address this, at speed test has been employed to detect subtle delay failures in manufacturing. However, the increasing process spread in advanced nanometer ASICs poses considerable challenges to predicting hardware performance from timing models. Performance verification in the...

Clustered voltage scaling is a power reducing method which does not affect the overall system performance. The main idea is to run gates on a non-critical path by a low-voltage supply. Since low-voltage gates are not able to drive high-voltage gates, level-converters are needed. In order to reduce the number of level-converters, which may cancel out the power savings, they are arranged in a clu...

Different types of software testing techniques and methods have been projected for taking care of these issues. Use of evolutionary algorithms for usual test generation has been an area of interest for many researchers. Genetic Algorithm (GA) is one such type of evolutionary algorithms. In this research paper, we current a study of Genetic Algorithm approach for addressing the different issues ...

The register element (flip-flop) is a basic building block to design any clocking system, which consists of the clock distribution tree and flip-flops. A large portion of the on chip power is consumed by the clocking system the total power consumption of the clocking system depends on both clocking distribution tree and also the register elements (flip-flops). The power consumption of register ...

This paper focuses on designing elliptic curve crypto-accelerators in GF (2m) that are cryptographically scalable and hold some degree of reconfigurability. Previous work in elliptic curve crypto-accelerators focused on implementations using projective coordinate systems for specific field sizes. Their performance, scalar point multiplication per second (kP/s), was determined primarily by the u...

In this paper, we present TxCF-Tree, a balanced tree whose design is optimized to support transactional accesses. The core optimizations of TxCF-Tree’s operations are: providing a traversal phase that does not use any lock and/or speculation, and deferring the lock acquisition or physical modification to the transaction’s commit phase; isolating the structural operations (such as re-balancing) ...

This paper starts with an initial gesture accepting the validity of many of the criticisms of modernity by some leading postmodern thinkers.From this initial position, it then evalutess the postmodernist positions themselves with regards to democracy and justice by paying careful attention to the arguments of these leading postmodernists Following this procedure, Lyotard's characterization of t...

Abstract— New design techniques with energy-delay characteristics that are superior to that of the synchronous timing and control approach are needed today because the throughput of systems realized with this method is limited by the power dissipation of nanometer scale devices and the power management strategies developed to insure that they do not exceed device thermal constraints. A circuit ...

Project management methodologies have been the most utilized management tools in today’s industry and the Critical Path Method considers the logical dependencies between related activities that may have to share common resources. This method has then been expanded to allow for the identification of resource-constrained activities and the size of those resources. They are usually called activity...