We present an automated temporal partitioning and design space exploration methodology that temporally partitions behavior speciications. We propose block-processing in the temporal partitioning framework for reducing the reconngura-tion overhead for partitioned designs. Block-processing is a technique used traditionally in the area of parallel compilers, for increasing the computation speed by...

This work extends an earlier manual design space exploration of our developed Selective Load Value Prediction based superscalar architecture to the L2 unified cache. After that we perform an automatic design space exploration using a special developed software tool by varying several architectural parameters. Our goal is to find optimal configurations in terms of CPI (Cycles per Instruction) an...

The system description language SystemC enables to quickly create executable specifications at adequate levels of abstraction for both hardware/software integration and fast design space exploration. Besides the modeling of a system, verification has become a dominant factor in circuit and system design. Since SystemC is a versatile language based on C++, testbenches at different abstraction le...

In this paper, we discuss an optimization-based approach for design space exploration to find limitations and possible trade-offs between performance metrics in analog circuits. The exploration guides the designer when making design decisions. For the design space exploration, which is expensive in terms of computation time, we use an optimization-based device sizing tool that runs concurrent o...

Design of a successful product requires evaluating many design alternatives in a limited design cycle time. This can be achieved through leveraging design space exploration tools and available computing resources on the network. This paper presents a parallel trade study architecture to integrate trade study clients and computing resources on a network using Web services. The parallel trade stu...

1 Computing Lower Bounds on Functional Units Before Scheduling1 Samit Chaudhuri2, Robert A. Walker3 Abstract|This paper presents a new polynomial-time algorithm for computing lower bounds on the number of functional units (FUs) of each type required to schedule a data ow graph in a speci ed number of control steps. A formal approach is presented that is guaranteed to nd the tightest possible bo...

Clusters of FPGAs are a promising environment for prototyping and evaluation of new MPSoC architectures with a large number of parallel cores. The high complexity of both the MPSoC and the FPGA cluster pose many challenges for the designer [1]. Tools like Synopsys Certify can be used to automatically partition designs on systems with a fixed communication infrastructure, still they do not addre...

We consider speeding up general-purpose applications with hardware accelerators. Traditionally hardware accelerators are tediously hand-crafted to achieve top performance. ASC (A Stream Compiler) simplifies exploration of hardware accelerators by transforming the hardware design task into a software design process using only ’gcc’ and ’make’ to obtain a hardware netlist. ASC enables programmers...

Software-intensive embedded systems are characterized by an increasing number of features that implement complex functionalities. To effectively manage this complexity, development processes in general, and model-based approaches in particular, support the development of such systems as model-based approaches have been considered a central design approach to deal with increasing complexity in s...

In studying the phenomenon of design we use models to envision mechanisms by which computers might support design. In one such model we understand design as guided movement through a space of possibilities. Design space explorers embody this model as mixed-initiative environments in which designers engage in exploration via human computer interaction. Constraint resolution provides a formal fra...