Digital LDO is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65nm CMOS achieved...

VLSI (Very Large Scale Integration) circuits are basic components of today’s complex digital systems. In order to realize dependable digital systems, VLSI circuits should be highly reliable. VLSI testing plays an important role in satisfying this requirement. VLSI testing is to check whether faults exist in a circuit, and it consists of two main phases: test generation and test application. In ...

* This work was done at Stanford-CRC and was supported by King Fahd University of Petroleum and Minerals. It was also supported by DARPA under contract No. DABT63-97-C-0024 (ROAR project). The authors would like to thank Chien-Mo Li and Chao-Wen Tseng for their help. Abstract Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two...

In this paper, we present a method of testing digital circuits during normal operation. The resources used to perform on-line testing are those which are inserted to alleviate the off-line testing problem. The off-line testing resources are modified such that during system operation they can also observe the normal inputs and outputs of a combinational circuit under test. The normal inputs to t...

An Efficient analog to digital interface (TDC/DTC) is presented. In particular, we explore time-based techniques for data conversion, which can potentially achieve significant reductions in power consumption while keeping silicon chip area will be very small. On the basis of a generic mixed-signal system the scaling difficulties of analog and mixed-signal circuits based on a signal representati...

A new short circuit power model for complex CMOS gates, " in Proc. An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation on CAD, " IEEE Trans. An analytical model for current, delay, and power analysis of submicron CMOS logic circuits, " IEEE Trans. Channel width tapering of serially connected MOSFET's with emphasis on power dissipation, " IEEE Tran...

This document defines the specific requirements for edge-to-edge emulation of circuits carrying Time Division Multiplexed (TDM) digital signals of the Plesiochronous Digital Hierarchy as well as the Synchronous Optical NETwork/Synchronous Digital Hierarchy over packet-switched networks. It is aligned to the common architecture for Pseudo Wire Emulation Edge-to-Edge (PWE3). It makes references t...

The quantum-dot cellular automata (QCA) is considered as an alternative tocomplementary metal oxide semiconductor (CMOS) technology based on physicalphenomena like Coulomb interaction to overcome the physical limitations of thistechnology. The decoder is one of the important components in digital circuits, whichcan be used in more comprehensive circuits such as full adde...

Lab Assignments Instrumentation Labs: Name of Lab Assignment: Lab 1 Introductory Experiments and Linear Circuits I [1] Lab 2 Linear Circuits II [2] Lab 3 Semiconductor Diodes [3] Lab 4 JFET Circuits I [4] Lab 5 JFET Circuits II [5] Lab 6 Op Amps I [6] Lab 7 Op Amps II [7] Lab 8 Op Amps III [8] Lab 9 LabVIEW Programming [9] Lab 10 Analog to Digital and Digital to Analog Conversion [10] Lab 11 Si...