We present an educational software package (Csim) used as a teaching tool to analyze the structure and behavior of a cache memory and to help the student in the design of cache memories for embedded systems. By means of an integrated software development environment, the user can create a program and explore its behavior (locality analysis). The student can observe the cache actions needed for ...

Received Jan 12, 2015 Revised Mar 28, 2015 Accepted Apr 22, 2015 Recently Low power custom memory design is the major issue for embedded designer. Micro wind and Xilinx simulator performs efficient cache simulation and high performances with low power consumption. SRAM efficiency analyzed with 6-T architecture design and analyzed the simulation performance for specific application. We have impl...

Methodologies for synthesis of stand-alone hardware modules from C/C++-based languages have been gaining adoption for embedded system design as an essential means to stay ahead of increasing performance, complexity, and time-to-market demands. However, using C to generate stand-alone blocks does not allow for truly seamless unification of embedded software and hardware development flows. This p...

Programming on a shared memory multiprocessor platforms in an efficient way is difficult as locked based synchronization limits the efficiency. Transactional memory (TM) is a promising approach in creating an abstraction layer for multi-threaded programming. However, the performance of TM is application-specific. In general, the configuration of a TM is divided into version management and confl...

Significant portion of cache energy in a highly associative cache is consumed during tag comparison. In this paper tag comparison is carried out by predicting both cache hit and cache miss using multistep tag comparison method. A partially tagged bloom filter is used for cache miss predictions by checking the non-membership of the addresses and hotline check for cache hit prediction by reducing...

Software development in the domain of embedded and deeply embedded systems is dominated by cost pressure and extremely limited hardware resources. As a result, modern concepts for separation of concerns and software reuse are widely ignored, as developers worry about the thereby induced memory and performance overhead. Especially object-oriented programming (OOP) is still little in demand. For ...

The increasing speed gap between processors and memory makes the design of memory hierarchy one of the critical issues in general purpose embedded systems. As memory requirements for embedded applications grow, especially in emerging area of handheld multimedia devices, cache memories become crucial for providing high performance and reducing power. This paper describes a performance evaluation...

Embedded processors are now widely used in system-on-chips. The computational power of such processors and their ease of access to/from other embedded cores can be utilized to test SoCs. The first step, naturally, is to test the processor itself and its memory partner, as all other SoC test activities require both. In this paper, an efficient test architecture is presented to achieve high quali...

We present an embedded processor based approach for Built-In Self-Test (BIST) and diagnosis of programmable logic and memory resources in Field Programmable Gate Arrays (FPGAs). The resources under test include the programmable logic blocks (PLBs), large random access memories (RAMs), and digital signal processors (DSPs) in all of their modes of operation. The approach is applicable to any FPGA...

The use of embedded DRAM technology has become widespread, especially in higher-end system designs, because of its superior performance, silicon area savings, and low power compared to discrete memory solutions. Traditionally, in cost-sensitive consumer applications, large memory arrays of 64 megabits and above were usually better suited to discrete commodity memory implementations. But as the ...