نتایج جستجو برای: fast adder
تعداد نتایج: 231887 فیلتر نتایج به سال:
Addition is one of the vital parts of any electronic system design because every electronic system needs this basic operation. Researchers have done a lot of work on various adders to optimise their performance. So, they found that Carry Save adder is best in terms of delay calculation and power consumption. That is why this proposed work use this adder. This paper is primarily focus on design ...
With the growing importance of electronic products in day-to-day life, the need for portable electronic products with low power consumption largely increases. In this paper, an area efficient high speed and low power Multiply Accumulator unit (MAC) with carry look-ahead adder (CLA) as final adder is being designed. In the same MAC architecture design in final adder stage of partial product unit...
This paper presents an improved 32-bit conditional sum adder. Due to architectural modification, the improved adder only selects and transmits carry signals; it therefore is named conditional carry adder (CCA). This 32-bit adder focuses on reducing the numbers of internal nodes and logical gates, while maintaining high speed. The 32-bit conditional sum adder uses 186 multiplexers, and the propo...
Adder being the basic hardware block of any arithmetic operation, the major constraint in the field of signal processors, data processors to perform any operations are highly dependent on the adder performance of the circuit. The gate level implementation of the carry select adder (CSLA) and modified carry select adder has significantly reduced the area and power consumption which replaced the ...
In this paper Modified Booth Multiplier (radix-4) implemented by various adder. Partial product generated by booth encoder is added by various adder techniques to compare the performance parameter of multiplier. Performance parameter like area, path delay, fan out, speed of multiplier. Multiplication is an important fundamental function in arithmetic logic operation. Since, multiplication domin...
The performance of existing adders varies widely in their speed and area requirements, which in turn sometimes makes designers pay a high cost in area especially when the delay requirements exceeds the fastest speed of a specific adder, no matter how small the difference is. To expand the design space and manage delay/area tradeoffs, we propose new adder architecture and a design methodology. T...
We consider the design of two well-known optimal timeadders: the “carry look-ahead” adder [6] and the “conditional sum”adder 1131.It is shown that 6 log,(n) 4 and 6 log2(n) + 2 test patterns suffice tocompletely test the n-bit carry look-ahead adder and the n-bit conditionalsum adder with respect to the single stuck-at fault model (for a given setof basic cells).
In this paper, we report a new design of an all-optical full-adder using two nonlinear resonators. The PhC-based consists three input ports (A, B, and C for bits), resonant cavities, several waveguides, output (for the SUM CARRY). Eight silicon rods rod composed doped glass form each cavity. well-known plane wave expansion technique is used to calculate photonic band structure. It shows wide ba...
This paper mainly presents Mixed Gate Diffusion Input Full Adder based on static CMOS inverter topology. In this proposed mixed Full Adder topology, GDI Full adders are followed by inverters in the long Full Adder chain to improve the performances as compared to conventional single topology Full adder chain. For any circuits reducing the speed and power dissipation are the important constraints...
In this paper, we have designed a new variable latency adder and its implementation of decimation filter. There are multiple ways to implement a decimationfilter. This filter design combination of CIC (cascaded-integrator-comb) filter and HB (half band) filter as the decimator filter to reduce the frequency sample rate conversion and detail of the implementation step to realize this design in h...
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