Transient faults are single-shot hardware errors caused by high energy particles from space, manufacturing defects, overheating, and other sources. Such faults can be devastating for securityand safetycritical systems. In order to mitigate these problems, software developers can add redundancy in various ways to their software systems. However, such redundancy is hard to reason about and corner...

We formulate a scheme for fault-tolerant quantum computation that works effectively against highly biased noise, where dephasing is far stronger than all other types of noise. In our scheme, the fundamental operations performed by the quantum computer are single-qubit preparations, single-qubit measurements, and conditionalphase CPHASE gates, where the noise in the CPHASE gates is biased. We sh...

The advances of deep submicron VLSI technology pose new challenges in designing robust systems, which can in principle be addressed by approaches established in fault-tolerant distributed systems research. This paper is the first step in an attempt to develop a very robust high-precision clocking system for hardware designs like systemson-chip for critical applications. It is devoted to the des...

We present simple lattice realizations of symmetry-protected topological phases with q-form global symmetries where charged excitations have q spatial dimensions. Specifically, we construct d space-dimensional models supported on a (d + 1)-colorable graph by using a family of unitary phase gates, known as multiqubit control-Z gates in quantum information community. In our construction, charged ...

Simulation of quantum systems that provide intrinsically fault-tolerant quantum computation is shown to preserve fault tolerance. Errors committed in the course of simulation are eliminated by the natural error-correcting features of the systems simulated. Two examples are explored, toric codes and non-abelian anyons. The latter is shown to provide universal robust quantum computation via simul...

Noise issues are becoming an important concern in digital systems due to the aggressive scaling trends in devices and interconnections. To address this problem a new noise-tolerant dynamic circuit technique suitable for dynamic logic styles is presented. Simulation results show that the proposed technique improves the ANTE by 3.4 and 2.8 over conventional dynamic True Single-Phase-Clock (TSPC) ...

A tool that simulates Stuck-Open Fault (SOF) is presented in this paper. In the nanoscale technology context, the behavior of Stuck-Open Fault is more affected by the high leakage currents. To analyze SOFs is necessary one pair of vectors, because the fault effect depends on previous state. This tool allows the circuit behavior analyses in the presence of SOFs in CMOS logic gates. Through the t...

Probabilistic-based methods have been used for designing noise tolerant circuits recently. In these methods, however, there is not any reliability mechanism that is essential for nanometer digital VLSI circuits. In this paper, we propose a novel method for designing reliable probabilistic-based logic gates. The advantage of the proposed method in comparison with previous probabilistic-based met...

Quantum computation has demonstrated advantages over classical for special hard problems, where a set of universal quantum gates is essential. Geometric phases, which have built-in resilience to local noise, been used construct with excellent performance. However, this advantage smeared in previous schemes. Here, we propose state-independent nonadiabatic geometric quantum-gate scheme that able ...