In many applications, offset of the OP-AMPs should be canceled to high accuracy be accomplished. In this work, an asymmetrical differential input circuit with active DC offset rejection circuit was implemented to minimize the systematic offset of the amplifier. The proposed OP-AMPs show that the systematic offset voltages is less than 80 μV. Keywords—component; formatting; style; styling; insert

in this paper first we try to analysis the behavior ofthe soas in the optical networks and then have proposed anumerical simple model to simulate the behavior of thesemiconductor optical amplifiers. after that by employing thismodel as inline amplifier for a dwdm optical system, we havesimulated the transmission of 10 channels with bit rate 10 gb/sup to distance 3970 km with rz-dpsk modulation ...

Sense amplifiers are one of the most vital circuits in the margin of CMOS memories. Their performance influences both memory access time and overall memory power dissipation. The existing Current-Mode Sense Amplifier coupled with a simplified read-cycle-only memory system has the ability to quickly amplify a small differential signal on the Bit-Lines (BLs) and Data-Lines (DLs) to the full CMOS ...

A low-voltage differential version of a high performance voltage follower is presented. The proposed circuit is very compact, and symmetric with respect to the input devices. Both differential input devices are enhanced by local shunt feedback, increasing the gain and, thus, reducing the output resistance for higher precision. The circuit has proved useful as a winner-take-all (WTA) circuit. It...

In this paper, a 10-Gb/s inductorless CMOS receiver front end is presented, including a transimpedance amplifier and a limiting amplifier. The transimpedance amplifier incorporates Regulated Cascode (RGC), active-inductor peaking, and intersecting active feedback circuits to achieve a transimpedance gain of 56 dB and a bandwidth of 8.27 GHz with a power dissipation of 35 mW. The limiting amplif...

A novel architecture and design approach which make it possible to boost the bandwidth slew-rate performance of operational transconductance amplifiers (OTAs) are proposed employed a low-power OTA with top-of-class small-signal large-signal figures merit (FOMs). The makes enhance gain, for given power consumption capacitive load, achieving more than an order magnitude better comparable conventi...

A High Swing Ultra-Low-Power Two Stage CMOS OP-AMP in 180 nm and 350nm Technology with 1.5V supply, is presented. Cascode technique has been used to increase the dc gain. The unity-gain bandwidth is also enhanced using a gain-stage in the Miller capacitor feedback path. It have 92.45 degree phase margin. The circuit has 94.866dB gain for 180nm. The power dissipation of the designed only is appr...

We propose capacitively driven low-swing global interconnect circuit using a receiver that utilizes magnetoelectric (ME) effect induced magnetization switching to reduce the energy consumption. Capacitively driven wire has recently been shown to be effective in improving the performance of global interconnects. Such techniques can reduce the signal swing in the interconnect by using a capacitiv...

In this paper a current mode very low voltage (LV) (1 V) and low power (LP) (21 μW) differential difference second generation current conveyor (CCII) is presented. The circuit is developed by applying the current sensing technique to a fully balanced version of a differential difference amplifier (DDA) so to design a suitable LV LP integrated version of the so-called differential difference CCI...