We propose a theoretical model to realize DNA made circuits based on in-vitro algorithms, to perform arithmetic and logical operations. The physical components of the resulting Arithmetic-Logic Unit are a variety of elements such as biochemical laboratories, test tubes and human operators. The advantage of the model is the possibility to perform arithmetic operations with huge binary numbers.

The implementation of Taylor models arithmetic may use floating-point arithmetic to benefit from the speed of the floatingpoint implementation. The issue is then to take into account the roundoff errors. Here, we assume that the floating-point arithmetic is compliant with the IEEE-754 standard. We show how to get tight bounds of the roundoff errors, and more generally how to get high accuracy f...

Carry free arithmetic using higher radix number system such as Redundant Binary Signed Digit can be used to meet the demand for computers operating at much higher speeds. The computation speed can also be increased by using the suitable design of adder and multiplier circuits. Fast RBSD adder cells suggested by Neelam Sharma in 2006 using universal logic are modified in the proposed design by r...

We consider computation trees (CTs) with operations $S \subset {+,-, *, DIV, DIV_c}$, where $DIV$ denotes integer division and $DIV_c$ integer division by constants. We characterize the families of languages $L \subset N$ that can be recognized over ${+,-, DIV_c}$ and ${+,-, *, DIV}$, resp. and show that they are identical. Furthermore, we prove lower bounds for CT's with operations ${+,-, DIV_...

This paper describes new vector indexing algorithms for Lattice Vector Quantization (LVQ). The techniques described apply to a large class of lattices such as Z n , A n , D n , D ++ n (including as special cases the Gosset Lattice E 8 , and the lattice of Barnes-wall 1 6), widely used in signal compression. Relying on a partitioning of the events sources, based on a notion of leaders, they allo...