In this paper, we investigate low voltage operation of master-slave flip-flops (MSFFs) for ultra-low power subthreshold CMOS LSI families. Static MSFF, which consists of NAND gates, shows the most stable operation, while dynamic MSFFs are unsuitable for low voltage operation because switching gates fail to operate at low voltage. Low voltage limitation of static MSFF depends on that of CMOS gat...

MOS current mode logic (MCML) is an emerging logic family which is gaining attention due to its high speed of operation, robust performance and presence of mere switching noise as compared to the CMOS logic family. In this paper we have compared universal gates using MCML and conventional CMOS in terms of power and propagation delay at 16-nm Technology node. Comparative analysis shows that MCML...

Polymorphic gates are unconventional circuit components that are not supported by existing synthesis tools. This article presents new methods for synthesis of polymorphic circuits. Proposed methods, based on polymorphic binary decision diagrams and polymorphic multiplexing, extend the ordinary circuit representations with the aim of including polymorphic gates. In order to reduce the number of ...

Abstract: Dynamic Domino logic circuits are widely used in modern digital VLSI circuits. Because it is simple to implement, low cost designs in CMOS Domino logic are presented. Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in logic such as domino circuits is used in high-performance applications. Domino gates typically consume higher dynamic switching and leakag...

Oscillating magnetic fields and field gradients can be used to implement single-qubit rotations and entangling multiqubit quantum gates for trapped-ion quantum information processing (QIP). With fields generated by currents in microfabricated surface-electrode traps, it should be possible to achieve gate speeds that are comparable to those of optically induced gates for realistic distances betw...

There are many articles and patents on the masking of logic gates. However, the existing publications assume that a masked logic gate switches its output no more than once per clock cycle. Unfortunately, this assumption usually does not hold true in practice. In this article, we show that glitches occurring in circuits of masked gates make these circuits susceptible to classical first-order DPA...