An advanced design methodology using a combination of behavioral models and transistor level models is presented in this paper. This methodology is very interesting for complex mixed-signal IC design, reducing the simulation time and improving the design flexibility. In order to validate the methodology proposed, a High-Speed Bandpass Continuous-Time Delta-Sigma Modulator is modeled. This modul...

In this paper, a procedure to calculate the sensitivity factors of the quiescent drain current of a field-effect transistor operating in the active region is presented. This one can be applied in conjunction with a general-purpose circuit simulator for bias circuits with bipolar junction transistors or field-effect transistors. We showed that the sensitivity factors of the quiescent drain curre...

In recent years, there have been major advances in integrated circuit technology which have both made feasible and generated great interest in electronic circuits which employ more than two discrete levels of signal. Such circuits, called multiple-valued logic circuits, offer several potential opportunities for the improvement of present VLSI circuit designs. In this paper, we give an overview ...

This paper presents a tutorial treatment of the fundamentals of noise in solid-state analog electronic circuits. It is written for upper division students andpracticing engineers who wish to gain a basic knowledge of the theory of electronic noise and techniques for low-noise circuit design. The paper presents an overview of noise fundamentals, a description of noise models for passive devices ...

Teaching the practical aspects of device and chip design in New Zealand presents many problems, including high manufacturing costs, long lead times, and the lack of local industry strength. Nonetheless, it is possible to overcome these issues. This paper describes the courses in these areas at the University of Canterbury, including a practical IC design project that has been running successful...

In this paper, we present our quantitative studies of the impact of 3D IC design on repeater usage. The repeater usage is estimated by the interconnect optimizer IPEM in the post-placement/ pre-routing stage, where the 2D and 3D placement are generated by state-of-art mixed-size placers mPL6 and mPL-3D. Experiments on a set of real industrial designs show that, through 3D placement, the total n...

Despite many advantages of Field-Programmable Gate Arrays (FPGAs), they fail to take over the IC design market from Application-Specific Integrated Circuits (ASICs) for high-volume and even medium-volume applications, as FPGAs come with significant cost in area, delay, and power consumption. There are two main reasons that FPGAs have huge efficiency gap with ASICs: (1) FPGAs are extremely flexi...

EXTENDED ABSTRACT The introduction of multilevel metalization processes brings new challenges to the design and fabrication of high yielding ICs. As much as 50% of yield loss in digital ICs can be attributed to the metalization stages of fabrication. This can be a particular problem when new process technologies such as multilevel interconnect are being introduced. The EYE tool addresses the pr...

There have been great advances in integrated circuits technology in recent years which have both made feasible and generated major interest in electronic circuits which employ more than two levels of signals. These circuits, called multiple valued logic circuits, offer several potential oppourtinities for the improvement of VLSI circuit designs. In this paper we review developments and potentia...