In the title mononuclear complex, [Cd(C(8)H(7)O(2))(2)(H(2)O)(2)], the Cd(II) atom possesses crystallographically imposed C(2) site symmetry, and is coordinated by four O atoms from two 4-methyl-benzoate ligands and two water mol-ecules, displaying a distorted octa-hedral geometry. The molecules are assembled via inter-molecular O-H⋯O hydrogen-bond inter-actions into a supra-molecular architect...

Network organizations and inter-organizational systems (IOS) have recently been the subjects of extensive research and practice. Various papers discuss technical issues as well as several complex business considerations and cultural issues. However, one interesting aspect of this context has only received adequate coverage so far, namely the ability of existing Enterprise Architecture Managemen...

The gate utilization of FPGAs and speed of emulation in multi-FPGA system are limited by the interconnection architecture and the number of pins. The time-multiplexing of interconnection wires is required for multi-FPGA systems incorporating several state-of-the-art FPGAs. This article proposes a circuit partitioning algorithm called SCheduling driven Algorithm for TOMi (SCATOMi) for multi-FPGA...

Clustering has become a common trend in very long instruction words (VLIW) architecture to solve the problem of area, energy consumption, and design complexity. Register-file-connected clustered (RFCC) VLIW architecture uses the mechanism of global register file to accomplish the inter-cluster data communications, thus eliminating the performance and energy consumption penalty caused by explici...

FPGA-based logic emulator with large gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporat...

FPGA-based logic emulator with large gate capacity generally comprises a large number of FPGAs. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several stateof-the-art FPGAs. This...

Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture which is the manner in which wires, FPGAs and Field-Programmable Interconnect Devices (FPIDs) are connected. Several routing architectures for MFSs have been proposed [Arno92] [Butt92] [Hauc94] [Apti96] [Vuil96]...

This paper introduces semi-user-level communication architecture, a new high-performance light-weighted communication architecture for inter-node communication of clusters. Different from traditional kernel-level networking architecture and user-level communication architecture, semi-user-level communication architecture removes OS kernel from its message-receiving path while reserves an OS tra...