In this paper, we propose a novel interconnect-aware pipeline synthesis system for array based reconfigurable architectures. The proposed system includes interconnect-aware pipeline scheduling, post-placement communication scheduling and others. The experiments on a number of real-life examples demonstrate usefulness of the proposed method. For scheduling, our proposed interconnectaware pipelin...

XU, JIAN. AC Coupled Interconnect for Inter-chip Communications. (Under the direction of Prof. Paul D. Franzon.) The scaling of integrated circuit (IC) technology demands high-speed, high-density and low-power input/output (I/O) for inter-chip communications. As an alternative scheme for conductive interconnects, AC coupled interconnect (ACCI) was proposed previously to meet these increasing I/...

This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the undesirable effects of on-chip inductance are higher interconnect coupling noise and substrate coupling, challenges for accurate extraction, the required modifications of the infrastructure of CAD tools, and the inevitably slowe...

long–term stability and oxidation resistance of aisi 439 ferritic stainless steel used as interconnects in solid oxide fuel cells can be improved by use of a protective coating. in this study the pack cementation method was employed to coat aisi 439 ferritic stainless steel with manganese. isothermal oxidation was conducted at 800 ºc for 200 hours in static air to investigate the role of coatin...

This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown that for unscaled global lines, inductance effects increase as technology scales while for the scaling scheme proposed by ITRS [1], interconnects become extremely resistive and, while inductance effects diminish with ...

This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown that for unscaled global lines, inductance effects increase as technology scales while for the scaling scheme proposed by ITRS [1], interconnects become extremely resistive and, while inductance effects diminish with ...

This paper reviews recent progress toward the monolithic, modular integration of microelectromechanical devices (MEMS) with electronics. The interconnect metallurgy poses a thermal budget limit on the processes that can be used to build the MEMS structures after the electronics are completed. In addition, the metal interconnect and inter-metal dielectric layers must be protected during the remo...

Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them allows fast design time, ease of routing, predictability of electrical parameters and good scalability. k-ary n-mesh topologies are candidate solutions for these systems, borrowed from the domain of off-chip interconnecti...

In this paper we have put forward an analytical model which can could accurately compute the on chip interconnect delay using distributed RLCG segments. With the increasing level of on chip integration the interconnect delay has acquired prominence for performance driven layout synthesis. Also in higher frequency range of the order of GHz , the effect of shunt conductance and inductance cannot ...