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We study planar orthogonal drawings of graphs and provide lower bounds on the number of bends along the edges. We exhibit graphs on n vertices that require (n) bends in any layout, and show that there exist optimal drawings that require (n) bends and have all of them on a single edge of length (n 2). This work nds applications in VLSI layout, aesthetic graph drawing, and communication by light ...

| Constrained Via Minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for twolayer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.

In this paper, we present an integrated computeraided design environment, the VAR (VHDL-based Array Reconfiguration) system, for the tasks of design, reconfiguration, simulation, and evaluation in an architecture modeled by VHDL. An easily diagnosable and reconfigurable two-dimensional defect-tolerant PE-switch lattice array is used as an example to illustrate the methodology of VAR. VAR allows...

The test problem increasingly affects system design process, related costs and time to market. Requirements from VLSI/WSI manufacturers are for fast and reliable testability tools, with the possibility of their introduction in early phases of design. This paper presents a global toolset architecture for testability analysis and test pattern generation. Three abstraction levels are considered in...

We present and analyze strategies which can be used for the parallel computation of large numbers of integrals which may be of diierent levels of diiculty. Paralleliza-tion on the integral level, which is generally used for large numbers of integrals, is combined with parallelization on the subregion level, which enables handling local integration diiculties within individual problems. This res...