The aim of this study was to obtain accurate angular positions and velocities from resolver signals; resolver-to-digital conversion (RDC) often adopts a phase-locked loop (PLL) as demodulation algorithm. However, signals come with quadrature errors harmonics, which lead severe reduction in PLL accuracy. conventional does not consider the impact error, bandwidth is much larger than fundamental f...

The voltage source converters (VSCs) are used to interface and control the renewable energy resources that integrated into power grids. However, a weak grid connection raises stability problem for synchronization of grid-feeding current-controlled VSCs (CCVSCs). This paper handles modeling controller design stabilizing CCVSCs. impedance modeling/shaping VSC has been recognized as an effective t...

A phase-locked-loop (PLL)-based frequency synthesizer incorporating a phase detector that operates on a windowing technique eliminates the need for a frequency divider. This new loop architecture is applied to generate the 1.573-GHz local oscillator (LO) for a Global Positioning System receiver. The LO circuits in the locked mode consume only 36 mW of the total 115-mW receiver power, as a resul...

This paper focuses on the power grid oscillation of grid-side converter (GSC) in doubly-fed induction generator (DFIG) caused by sub-synchronous (SSO), and designs a measure to improve output quality GSC. Firstly, influence mechanism multipath disturbance GSC under SSO is sorted out, factors action modes are clarified. Secondly, estimation phase-locked loop (PLL) control strategy calculation pr...

Grid-connected converters under weak grid conditions could present instabilityassociated with the synchronization elements and not directly current control loop. The impedance-based stability criterion is an effective tool to address problem. To solve negative effect of synchronous reference frame phase-locked loop (SRF-PLL) on conditions, a structure prefilter, based filtered quadrature signal...

Technology advances have made gigabit signal a viable and attractive. A method to design IEEE 1394 based 1GHz Phase Locked Loop (PLL) system as frequency synthesizer with Low Phase Noise is proposed. A complementary LC oscillator is used to generate the 1GHz oscillation frequency and is divided into lower frequency clock by the feedback frequency divider. The architecture is type II third order...

This paper deals with the use of shunt active filter to compensate current perturbations produced by non linear loads. To perform the identification of disturbing currents, the so called Instantaneous Active and Reactive Power Method (pq) is used. A Phase Locked Loop (PLL) circuit, locked to the fundamental frequency of the system voltage, is also introduced for eventual mains voltages perturba...

The traditional VSG strategy does not consider the negative sequence component, which will lead to current imbalance and power oscillation under unbalanced voltage. Several improved control strategies of are usable for operating voltage nowadays. These usually require a complex PLL (phase-locked loop) detect components, reference generator convert references references. This paper proposes an V...

We report a 40-GHz harmonically and regeneratively FM mode-locked erbium fiber laser with a phase-locked loop (PLL) circuit operating in the 1.6 m region. The oscillation wavelength was extended to the L-band by using a 15 m erbium-doped fiber with an Er concentration of 3500 ppm as a gain medium. As a result, a 770 fs transform-limited Gaussian pulse with a 14 mW output power was successfully...

<p>The voltage-controlled oscillator (VCO) is the primary device in phase-locked loop (PLL) to produce local frequency. The excessive phase noise of VCOs cause PLL performance loss. This paper proposes design and optimization low power consumption for a 180 nm N-channel metal-oxide semiconductor NMOS VCO applications with P-channel PMOS varactors spiral inductors. At 2 V supply voltage, o...