A Built-In Self-Test (BIST) approach for the programmable Input/Output (I/O) buffers in Field Programmable Gate Arrays (FPGAs) is presented. The I/O buffers are tested for their various modes of operation along with their associated routing sources. A general BIST architecture, applicable to any FPGA, is presented along with the features and limitations of the approach. Experimental results are...

compute chip: Control, test, and bring-up infrastructure R. A. Haring R. Bellofatto A. A. Bright P. G. Crumley M. B. Dombrowa S. M. Douskey M. R. Ellavsky B. Gopalsamy D. Hoenicke T. A. Liebsch J. A. Marcella M. Ohmacht The Blue Genet/L compute (BLC) and Blue Gene/L link (BLL) chips have extensive facilities for control, bring-up, self-test, debug, and nonintrusive performance monitoring built ...

This paper presents an attempt of using intelligent agents for testing and repairing a distributed system, whose elements may or may not have embedded BIST (Built-In Self-Test) and BISR (Built-In Self-Repair) facilities. It also discusses a few possible solutions for remotely managing the agent society, including the devices, agents, tests and repair processes. The agents are software modules t...

Aim of this paper is to present a self-testable FIFO memoN macrocell, which can be embedded into larger devices. A dual port RAM-Ope FIFO has been designed. A new test procedure for the macrocell has been defined aiming ar detecting all possible faults in the control logic and the RAM cell. Given such a test procedure the appropriate Built-h Self Test archirecture has been defined, independentl...

This paper presents the implementation of online test scheme for RFID memories based on Memory Built in Self Test (MBIST) architecture. This paper also presents the, Symmetric transparent version of March SS algorithm, implementation of Memory BIST. The comparison between the different march algorithms and the advantage of the March SS algorithm over all other is also presented. The solution wa...

In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not completely random pattern testable, the test programs have to generate deterministic patterns after random testing. Usually the random test part of the program requires long run times whereas the part for deterministic testing has ...

Electronic systems have become highly complex, which results in a dramatic increase of both design and production cost. Recently a core-based system-on-chip (SoC) design methodology has been employed in order to reduce these costs. However, testing of SoCs has been facing challenges such as long test application time and high temperature during test. In this thesis, we address the problem of mi...

Recent studies show that at-speed functional tests are better for nding realistic defects than tests executed at lower speeds. This advantage has led to growing interest in design for at-speed tests. In addition, time-to-market requirements dictate developments of tests early in the design process. In this paper, we present a new methodology for synthesis of at-speed self-test programs for micr...

Background & Aims: Recent studies have indicated memory dysfunction in individuals with obsessive compulsive disorder (OCD). The present study aimed to examine the relationship between cognitive selfawareness and episodic memory performance in patients with OCD and healthy individuals. Methods: In the present study, 30 patients with OCD and 30 normal individuals in the Shiraz Professional C...

A deterministic partitioning technique for fault diagnosis in Scan-Based BIST is proposed. Properties of high quality partitions for improved fault diagnosis times are identified and low cost hardware implementations of high quality deterministic partitions are outlined. The superiority of the partitions generated by the proposed approach is confirmed through mathematical analysis. Theoretical ...