With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. Some current designs already integrate extremely large on-chip caches, and there are aggressive next-generation designs that attempt to also integrate the memory controller, coherence hardware, and network router all ont...

Hewlett-Packard University Memorial Auditorium, August 8-10, 1993. In the five years since its inception, the annual symposium has grown into one of the most popular and fun conferences for chip designers, architects, and users, The informal atmosphere at the beautiful Stanford University campus in late summer, coupled with technical presentations on the latest “product-oriented” chips, seem to...

in this study, effect of two genotype imputation strategies, relatedness between reference panel and test populations and minor allele frequency on imputation error rate were examined with using a stochastic simulated population. reference panel and test populations were composed of 1,000 and 500 individuals, respectively. individuals in the reference panel were genotyped with using a high and ...

Constructing highly detailed 3-D models of large complex sites using range scanners can be a time consuming manual process. One of the main drawbacks is determining where to place the scanner to obtain complete coverage of a site. We have developed a system for automatic view planning called VuePlan. The system proceeds in two distinct stages. In the initial phase, the system is given a 2-D sit...

—An asynchronous implementation of the ARM microprocessor has been developed using an approach based on Sutherland's Micropipelines [1]. The design allows considerable internal asynchronous concurrency. This paper presents the rationale for the work, the organization of the chip, and the characteristics of the prototype silicon. The design displays unusual properties such as nondeterministic (b...

The computer architecture of Single-chip multiprocessor (SCMP) is one of important research topics in developing the next-generation of computer hardware. A verification environment in the SCMP architecture, base of RISC microprocessor, acts as a functional verification simulator that elaborates its functions. This paper reports a simulation of the operational behavior in terms of function unit...

In [2] Bounded Model Checking with the aid of satis ability solving (SAT) was introduced as an alternative to traditional symbolic model checking based on solving xpoint equations with BDDs. In this paper we show how bounded model checking can take advantage of specialized optimizations. We present a bounded version of the cone of in uence reduction that works very well for verifying safety pro...

This paper compares the performance characteristics of the Alpha 21164 to the previous-generation 21064 microprocessor. Measurements on the 21164-based AlphaServer 8200 system are compared to the 21064based DEC 7000 server using several commercial and technical workloads. The data analyzed includes cycles per instruction, multiple-issued instructions, branch predictions, stall components, cache...

LEADING VLSl CHIP and digital system manufacturers report an increasing number of undetected temporary faults that cause permanent damage in general-purpose microprocessor-based systems.’ Clearly, modern VLSI circuits require higher reliability as traditional means of protection against temporaiy faults become insufficient. This need renewed interest in self-checking circuits for on-line error ...