Tag reduction is an approach to save energy of the cache system in a processor. Our previous work described that it can save more energy on a Chip Multiprocessor (CMP) than on a single-core processor. In this paper, we further investigate the problem on balancing energy saving and performance overhead when tag reduction is used for the low power Chip Multiprocessor (CMP). We first introduce the...

Many real-world networked systems exhibit a multicore-periphery structure, i.e., multiple cores, each of which contains densely connected elements, surrounded by sparsely connected elements that define the periphery. Identification of the multiple-periphery structure can provide a new handle on structures and functions of various complex networks, such as cognitive and biological networks, food...

In this paper, we present the MorphoSys reconfigurable architecture, which combines a configurable array of processing elements with a RISC processor core. We provide a system-level model, describing the array architecture and the inter-connection network. We give several examples of applications that can be mapped to the MorphoSys architecture. We also show that MorphoSys achieves performance ...

We present a novel test methodology for testing IP cores in SoCs with embedded processor cores. The methodology uses the processor core to run a test program to deliver test patterns to the target IP cores in the SoC and analyze the test responses. The test program can also use the processor core to generate test patterns. This provides tremendous flexibility in the type of patterns that can be...

A multi-core cluster is a cluster composed of numbers of nodes where each node has a number of processors, each with more than one core within each single chip. Cluster nodes are connected via an interconnection network. Multi-cored processors are able to achieve higher performance without driving up power consumption and heat, which is the main concern in a single-core processor. A general pro...

This final technical report was prepared for the Air Force Research Laboratory, under award #FA8750-08-1-0024, titled “MultiCore Hardware Experiments in Software Producibility,” responsible program officer, Steven Drager. This report details our findings when taking heterogenous systems software, designed for a distributed environment, and running it on a single-core, and later multi-core, comp...

A novel GF(p) crypto processor core architecture is presented in this paper. The core is used to implement GF(p) Elliptic Curve Cryptosystem (ECC). The architecture is such that a single core can be used to implement ECC or alternatively a two core solution can be adopted. As a result, the core architecture allows the exploitation of the parallelism that exists in elliptic curve point addition ...

The Next Generation Microprocessor (NGMP) is a SPARC V8(E) based multi-core architecture that provides a significant performance increase compared to earlier generations of European space processors. The NGMP is currently in development at Aeroflex Gaisler Göteborg, Sweden, in activities initiated by the European Space Agency (ESA). The presentation and paper describes the baseline NGMP archite...

TimeTrial is a performance monitoring tool designed to enhance the understanding of how and why a streaming data application is performing when deployed on an architecturally diverse computer. A challenge that exists in architecturally diverse systems is that different computing platforms (e.g., processor core, FPGA) have different clocks, and the notion of time as measured on one platform does...

To pave the way for Byzantine fault-tolerant (BFT) systems that can exploit the potential of modern multi-core platforms, we present a new parallelization scheme enabling BFT systems to scale with the number of available cores and to provide the performance required by critical central services. The main idea is to organize parallelism around complete instances of the underlying multi-phase BFT...