This paper explores a simple and efficient baseline for text classification. Our experiments show that our fast text classifier fastText is often on par with deep learning classifiers in terms of accuracy, and many orders of magnitude faster for training and evaluation. We can train fastText on more than one billion words in less than ten minutes using a standard multicore CPU, and classify hal...

We consider a new generation of Commercial-Off-The-Shelf (COTS) Software Routers (SRs), able to effectively exploit multi-core/CPU hardware platforms. This choice was mainly driven from the fact that SRs are one of the few platforms including power management features, and that can be easily customized. Our main objective is to evaluate and to model the impact of power saving mechanisms, genera...

A modern high-performance multi-core processor has large shared cache memories. However, simultaneously running threads do not always require the entire capacities of the shared caches. Besides, some threads cause severe performance degradation by inter-thread cache conflicts and shortage of capacity on the shared cache. To achieve high performance processing on multi-core processors, effective...

Mesh free parallel implementations using multi-core processors are discussed. Particularly, parallelization of the MLPG and SPEM are shown. The appropriate strategies to correctly parallelize the mesh free methods are discussed. Parallel versions run up to 1.96 times faster on dual-core processor and 3.78 on quad-core processor when compared to the sequential one.

Current XPath processors use direct approach to query evaluation which is quite inefficient in some cases and usually implemented serially. This may be a problem in case of processing complex queries on large documents. We propose algorithms and XML indexing techniques which are more efficient and which can utilize standard parallel templates. Our implementation is highly scalable and outperfor...

When computer architects re-invented parallelism through multi-core processors, application parallelization became mandatory. The challenge of “mass-parallelization” forced the software community to react quickly. Unfortunately, instead of tackling such a large-scale problem in a systematic way, we have rather experienced various random search, non-portable and non-reusable approaches. We belie...

Software transactional memory (STM) guarantees that a transaction, consisting of a sequence of operations on the memory, appears to be executed atomically. In practice, it is important to be able to run transactions together with nontransactional legacy code accessing the same memory locations, by supporting privatization. Privatization should be provided without sacrificing the parallelism off...

The range of verification problems that can be solved with logic model checking tools has increased significantly in the last few decades. This increase in capability is based on algorithmic advances, but in no small measure it is also made possible by increases in processing speed and main memory sizes on standard desktop systems. For the time being, though, the increase in CPU speeds has most...

We present a block structured orthogonal factorization (BSOF) algorithm and its parallelization for computing the inversion of block p-cyclic matrices. We aim at the high performance on multicores with GPU accelerators. We provide a quantitative performance model for optimal host-device load balance, and validate the model through numerical tests. Benchmarking results show that the parallel BSO...

Recent research has highlighted the potential benefits of single-ISA heterogeneous multicore processors over cost-equivalent homogeneous ones, and it is likely that future processors will integrate cores that have the same instruction set architecture (ISA) but offer different performance and power characteristics. To fully tap into the potential of these processors, the operating system must b...