Estimation of L norms of Fourier multipliers is known to be hard. It is usually connected to some interesting types of PDE, see several such PDE for several Fourier multipliers on the line in a recent paper of Kalton and Verbitsky [13]. Sometimes, but much more rarely, one can establish sharp L estimates for Fourier multipliers in several variables. Riesz transforms are examples of success. The...

New bit-parallel dual basis multipliers using the modified Booth s algorithm are presented. Due to the advantage of the modified Booth s algorithm, two bits are processed in parallel for reduction of both space and time complexities. A multiplexer-based structure has been proposed for realization of the proposed multiplication algorithm. We have shown that our multiplier saves about 9% space co...

In this paper, we propose an architecture/methodology for making FPGAs suitable for integer as well as variable precision floating point multiplication. The proposed work will of great importance in applications which requires variable precision floating point multiplication such as multi-media processing applications. In the proposed architecture/methodology, we propose the replacement of exis...

ÐThis paper deals with the computation of reciprocals, square roots, inverse square roots, and some elementary functions using small tables, small multipliers, and, for some functions, a final alargeo (almost full-length) multiplication. We propose a method, based on argument reduction and series expansion, that allows fast evaluation of these functions in high precision. The strength of this m...

DSP applications are rich in multiplication operations. Hence there is a growing need in improving the efficiency of multipliers. To improve the performance of multipliers, reconfiguration is introduced. In this paper, reconfiguration is introduced in the form of one level recursive architecture to the existing modified booth multiplier (MBM). It provides reconfigurable modes that satisfy multi...

This paper presents, low power signed and unsigned fixed-width multipliers using the column bypassing technique with carry save adder array structure. We have decomposed the partial products into two parts and executed them in parallel to reduce the delay of proposed fixed-width array multiplier. The proposed multiplier reduces the power consumption by skipping the unwanted switching activity w...

Until recently, verifying multipliers with formal methods was not feasible, even for small input word sizes. About two years ago, a new data structure, called Multiplicative Binary Moment Diagram (*BMD), was introduced for representing arithmetic functions over Boolean variables. Based on this data structure, methods were proposed by which verification of multipliers with input word sizes of up...

For many applications from the areas of cryptography and coding, finite field multiplication is the most resource and time consuming operation. We have designed and optimized four high performance parallel GF (2) multipliers for an FPGA realization and analyzed the time and area complexities. One of the multipliers uses a new hybrid structure to implement the Karatsuba algorithm. For increasing...

Multi-moduli architectures are very useful for reconfigurable digital processors and fault-tolerant systems that utilize the Residue Number System (RNS). In this paper we propose a novel architecture for configurable modulo 2±1 multipliers. It uses the modified Booth encoding of the input operand for deriving the required partial products and an adder tree followed by a sparse parallel-prefix f...