Newer and newer parallel architectures being developed raise a strong demand for high-level and programmer-friendly parallel tools. We show some results regarding mining of association rules, a well-known Data Mining algorithm, which we ported from sequential to parallel within the PQE2000/SkIE environment. The main goals achieved are the low eeort spent in parallelizing the code, the machine i...

Bulk synchronous parallel architectures o er the prospect of achieving both scalable parallel performance and architecture independent parallel software. They provide a robust model on which to base the future development of general purpose parallel computing systems. In this paper we theoretically and experimentally analyse the e ciency with which a wide range of important scienti c computatio...

A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. &#10The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of fu...

Modern complex embedded applications inmultiple application fields impose stringent and continuously increasing functional and parametric demands. To adequately serve these applications, massively parallel multi-processor systems on a single chip (MPSoCs) are required. This paper is devoted to the design of scalable communication architectures of massively parallel hardware multi-processors for...

SUMMARY The convergence rate of standard multigrid algorithms degenerates on problems with stretched grids or anisotropic operators. The usual cure for this is the use of line or plane relaxation. However, multigrid algorithms based on line and plane relaxation have limited and awkward parallelism and are quite diicult to map eeectively to highly parallel architectures. Newer multigrid algorith...

A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of func...

The increasing computational needs of parallel applications inevitably require portability across popular parallel architectures, which are becoming heterogeneous. The lack of a common parallel framework results in divergent code bases, difficulty in porting, higher maintenance cost, and, thus difficulty achieving optimal performance on target architectures. Our paper examines two representativ...

The use of series architecture nowadays is mainly on hybrid buses. In comparison with series-parallel and parallel architectures, which are usually exploited medium-size cars, the allows achieving internal combustion engine higher efficiency. downside this architecture, due to a double energy conversion (i.e., mechanical converted in electrical again energy), that additional losses introduced. ...

In this paper, high-efficient lifting-based architectures for the 5/3 forward and inverse discrete wavelet transform (DWT) are proposed. The proposed parallel and pipelined architecture consists of a horizontal filter (HF) and a vertical filter (VF). The system delays of the proposed architectures are reduced. Filter coefficients of the biorthogonal 5/3 wavelet low-pass filter are quantized bef...