System on Chip (SOCJ design in theforthcoming billion transisror era will involve the integration of numerous hererogeneous semiconductor intellectual proper@ ( I f ) blocks. Some of the main problems in the ultra deep sub micron technologies characterized by gate lengths in rhe range of 50-100 nm arise from non-scalable global wire delays, failure ro achieve global synchronization, errors due ...

Most of today's SOCs (Systems on Chips) are made of manufactured IP's interconnected through complex networks. The IP's have ordinarily been validated by various techniques (simulation, test, formal verification) and the key problem remains the validation of the communication infrastructure. This paper addresses the formal verification of such Networks on Chips by means of a mechanized proof to...

Networks-on-Chip is emerging as a communication platform for future complex SoC designs, composed of a large number of homogenous or heterogeneous processing resources. Most SoC platforms are customized to the domainspecific requirements of their applications, which communicate in a specific, mostly irregular way. The specific but often diverse communication requirements among cores of the SoC ...

Next-generation optoelectronic devices and photonic circuitry will have to incorporate on-chip compatible nanolaser sources. Semiconductor nanowire lasers have emerged as strong candidates for integrated systems with applications ranging from ultrasensitive sensing to data communication technologies. Despite significant advances in their fundamental aspects, the integration within scalable phot...

The rapid growth of brain-inspired computing coupled with the inefficiencies in the CMOS implementations of neuromrphic systems has led to intense exploration of efficient hardware implementations of the functional units of the brain, namely, neurons and synapses. However, efforts have largely been invested in implementations in the electrical domain with potential limitations of switching spee...

This paper presents a novel and efficient mapping algorithm, called Citrine. It generates a set of mappings which have nearly minimum possible distance between related cores results in reduction of communication cost in Network-on-Chip (NoC), while improving other performance metrics. Comparison of the communication cost results makes it obvious that final solutions found by our proposed approa...

Embedded systems sometimes experience transient overloads due to workload bursts. Such systems have to be designed to take timely reactions at the occurrences of unexpected situations. The development of smart techniques that focus the available computing power on these urgent events and at the same time, slow down the processing frequency during inactive periods could be the key for preserving...

The aim of this Chapter is to present a highly flexible reconfigurable NoC solution for commercial FPGAs on one side, and on the other side, to provide an innovative approach for fast NoC emulation. The reconfigurable on-chip communication solution that is proposed in this chapter is capable of being reconfigured by means of adapting routers, network interfaces and cores themselves. The main di...

Modern iterative channel code decoder architectures have tight constrains on the throughput but require flexibility to support different modes and standards. Unfortunately, flexibility often comes at the expense of increasing the number of clock cycles required to complete the decoding of a data-frame, thus reducing the sustained throughput. The Network-on-Chip (NoC) paradigm is an interesting ...

Network-on-chip (NoC) is considered as a promising paradigm to overcome the communication bottleneck of future multicore systems. As a basic component in on-chip router, arbiter has a big impact on the performance of router. In this paper, we propose a novel dynamically adaptive arbiter which is based on the round robin mechanism. The proposed arbiter detects buffer status of input ports and ch...