نتایج جستجو برای: pipelining

تعداد نتایج: 1926  

Journal: :Research Journal of Applied Sciences, Engineering and Technology 2015

2012
Kulvir Singh Dilip Kumar Wen-Chang Yeh Hwang-Cherng Chow W. C. Yen C. S. Wallace Soojin Kim Kyeongsoon Cho Harish M Kittur

This paper presents a high-speed and low area 16 ×16 bit Modified Booth Multiplier (MBM) by using Carry Select Adder (CSA) and 3-stage pipelining technique. CSA improves the performance of MBM and pipelining technique reduces the delay time. Using these techniques, the delay is reduced by 56% and the numbers of SLICES and LUT's are reduced by 4% as compared to high speed MBM. The multiplie...

Journal: :IEICE Transactions 2005
Jeong-Gun Lee Suk-Jin Kim Jeong-A Lee Kiseon Kim

This paper presents a new asynchronous FIFO design to reduce forward latency in a linear structure. The operation mode for each cell can be reconfigured dynamically as either of the two schemes, wave pipelining or handshaking, according to the data flow in the FIFO. The adoption of wave pipelining to the conventional self-timed FIFO can reduce the overhead of the handshaking as well as latching...

1994
Nelson Luiz Passos Edwin Hsing-Mean Sha Steven C. Bass

? Multi-dimensional (MD) systems are widely used in scientiic applications such as image processing, geophysical signal processing and uid dynamics. Earlier scheduling methods in synthesizing MD systems do not explore loop pipelining across diierent dimensions. This paper explores the basic properties of MD loop pipelining and presents an algorithm, called multi-dimensional rotation scheduling,...

1995
David Wessels James Cook Jon C. Muzio

In this paper, we consider the use of a limited pipelining scheme in conjunction with a gate resizing technique to improve the optimal clock speed of a combinational logic block. Gate resizing is restricted to a small subset of the circuit, and target gates are identiied using a delay sensitivity metric introduced here. 1 Abstract In this paper, we consider the use of a limited pipelining schem...

1998
Johan Janssen Henk Corporaal Ireneusz Karkowski

Software pipelining is a powerful and efficient scheduling technique for exploiting instruction level parallelism in loops, it results in high performance but it increases the register requirements. Two methods are available to reduce the register requirements: increase the schedule length or insert spill code. Traditionally instruction scheduling and register allocation are applied in separate...

2006
GEORGE-OTHON GLENTIS KRISTINA GEORGOULAKIS

In this paper, novel pipelined architectures for the implementation of the frequency domain linear equalizer are presented. The Frequency Domain (FD) LMS algorithm is utilized for the adaptation of equalizer coefficients. The pipelining of the FD LMS linear equalizer is achieved by introducing an amount of time delay into the original adaptive scheme, and following proper delay retiming. Simula...

2001
Bernd O. Christiansen Klaus E. Schauser Malte Münke

Thin client compression (TCC) achieves the best compression efficiency for sequences of synthetic images. This paper presents a streaming version of TCC (STCC) that almost fully retains the excellent compression efficiency of the original algorithm. When sending images over low-bandwidth networks, STCC dramatically reduces end-to-end latency by pipelining rows and overlapping the compression, t...

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