We present a novel and efficient thermal sensor design methodology. The growing demand for power management on VLSI systems drives the need for accurate thermal sensors. Conventional design techniques for on-chip thermal sensors in nanometer technologies consume expensive design iterations and result in increased power consumption and area overhead. Power-efficient, high-sensitivity thermal sen...

In this paper, a CMOS low power amplifier based on a high-quality active inductor and implemented by using 0.25-μm 1P5M CMOS standard technology is presented. The amplifier achieves power gain (S21) of 18dB within the -3dB cutoff frequency, bandwidth of 1.3GHz, and power consumption of 18mW under 2.5V power supply in 188 × 174μm silicon area. The input third-order intercept point (IIP3) and the...

We propose a time-to-digital converter (TDC) using a charge pump and a SAR-ADC. With this architecture, high time resolution is attainable by increasing the charging current or reducing the sampling capacitance. Thus, the resolution limitation in a delay-chain TDC does not exist. We propose to use a SAR-ADC attributed to its characteristics of compact structure, scalability, low power consumpti...

This paper proposes a advanced method of extended true-single-phase-clock (E-TSPC) based divide-by-2/3 counter design for providing low supply voltage and low power consumption. The counting logic and the mode selection control can be desingned by the help of single transistor using wired OR method. The proposed method mainly focus on for saving power consumption and it reduces the critical pat...

With the ever-growing use of computers and rapid growth in chip fabrication technology, the performance of CPU doubled approximately every 18 months by Moore’s law and CPU clock speed increased exponentially for better performance guarantees. The advancement in IC technology led to the increase in number of chips on a processor which in turn resulted in more power consumption. The basic power c...

In this paper, a new low-VDD CMOS bandgap reference circuit with small layout area and low power consumption is proposed. The proposed circuit delivering its output voltage below 1V has its Proportional-To-Absolute-Temperature (PTAT) term compensated by the Complementary-proportional-To-AbsoluteTemperature (CTAT) voltage thereby suppressing a change in its output voltage regardless of temperatu...

The phase frequency detector has been designed for high frequency phase locked loop in 180 nm CMOS Technology with 1.8V supply voltage using CADENCE Spectre tool. A Virtuoso Analog Design Environment and Virtuoso LayoutXL tools of Cadence have used to design and simulate schematic and layout of phase frequency detector respectively. Architecture of phase frequency detector (PFD) has simulated t...

Power-aware computing aims either to maximise the performance of a system under certain constraints on its power consumption and dissipation or, dually, to reduce power consumption in order to meet desired performance or throughput targets. This area is currently gaining importance due to the increasing usage of portable, mobile and hand-held electronic devices. In this paper we illustrate the ...

Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...