Using a persistent multicomputer object store should greatly simplify the writing of distributed memory parallel programs operating on irregular, object-structured data, by removing from the programmer the burden of managing data referencing, distribution and coherency. In this report we explore the development of such a program using the HeROD persistent multicomputer object store, in a comput...

In this paper we present a natural language lexical analysis program generator (NLlex) that looks like Unix lex extended with morphological analysis and other Natural Language (NL) elements. NLlex generates a C program which is linked with a morphological analyzer and with other modules, in order to produce a NL processor. As a particular case, NLlex can generate modules to work: as a lexico-mo...

Instruction scheduling is essential for the eecient operation of today's and to-morrow's processors. It can be stated easily and declaratively as a logic program. Consistency techniques embedded in logic programming enable the eecient solution of this problem. This paper describes an instruction scheduling program for the Motorola 88100 RISC processor, which minimizes the number of pipeline sta...

Load balancing involves assigning to each processor work proportional to its performance, thereby minimizing the execution time of a program. Although static load balancing can solve many problems (e.g., those caused by processor heterogeneity and nonuniform loops) for most regular applications, the transient external load due to multiple users on a network of workstations necessitates a dynami...

A xed-point C compiler is developed for convenient and efcient programming of TMS320C50 xed-point digital signal processor. This compiler supports the `fix' data type that can have an individual integer word-length according to the range of a variable. It can add or subtract two data having di erent integer word-lengths by automatically inserting shift operations. The accuracy of xed-point mult...

Because processor architectures are increasingly complex, it is increasingly difficult to embed accurate machine models within compilers. As a result, compiler efficiency tends to decrease. Currently, the trend is on top-down approaches: static compilers are progressively augmented with information from the architecture as in profile-based, iterative or dynamic compilation techniques. However, ...

The evolvable multiprocessor (EvoMP), as a novel multiprocessor system-on-chip (MPSoC) machine with evolvable task decomposition and scheduling, claims a major feature of low-cost and efficient fault tolerance. Non-centralized control and adaptive distribution of the program among the available processors are two major capabilities of this platform, which remarkably help to achieve an efficient...

We describe the analysis of an on-line pattern-recognition algorithm to dynamically control the configuration of the L1 data cache of a high-performance processor. The microarchitecture achieves higher performance and energy saving due to the accommodation of operating frequency, capacity, set-associativity, line size, hit latency, energy per access, and chip area to program workload and ILP. W...

This paper deals with two-processor scheduling for general acyclic SWITCH-less program nets with random node firing times. First, we introduce a hybrid priority list L∗ that has been shown to generate optimal schedules for the acyclic SWITCH-less program nets with unity node firing times, of which AND-nodes possess at most single input edge. Then considering the factors of existence of the AND-...