In this work, we have formalized and verified a hardware implementation of the Table-Driven algorithm for the floating-point exponential function. We have used a hierarchical approach enabling the verification of this function from the gate level implementation up to a behavioral specification adapted from the high level algorithmic description written by Harrison [3].

A technique is introduced to enable the simulation of floating-gate transistors within standard analogue circuit simulators, such as SPICE. This technique can be used in all types of circuit simulations, ranging from DC sweeps to charge-modification scenarios. The technique is then used to simulate several analogue circuits, the results of which show strong agreement with identical circuits fab...

We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is verified on the gate level against a formal description of the IEEE standard by means of the theor...

In this paper we present an ultra low-voltage bidirectional and continuous time current mirror based on clocked semi-floating-gate transistors. The current mirror may be used with supply voltages down to 250 mV and frequencies up to several hundred MHz. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90 nm TSMC CMOS process.

A novel and versatile implementation for analog defuzzification with fixed singleton coefficienls is introduced. It is based on differential pairs with multiple input floating gate transistors and on Gilben uanslinearcells. The singlcton cocfficients are determined by relative capacitance values. Experinlental results of a breadboard prototype that verify the proposed schemc are shown.

The extracellular ionic microenvironment has a close relationship to biological activities such as by cellular respiration, cancer development, and immune response. A system composed of ion-sensitive field-effect transistors (ISFET), cells, and program-controlled fluidics has enabled the acquisition of real-time information about the integrity of the cell membrane via pH measurement. Here we ai...

The paper presents Gate Transfer Level (GTL) as a general framework for synthesis of industrial complexity asynchronous quasi-delay-insensitive (QDI) circuits. The GTL flow automatically provides the finest degree of pipelining (gate-level) resulting in extremely high-performance designs. Automatic gate level pipelining is not possible for synchronous design due to the stage balance problem and...

The performance of carbon nanotube field-effect transistors is analyzed, using the nonequilibrium Green’s function formalism. The role of the inelastic electron-phonon interaction on the both on-current and gate delay time of these devices is studied. For the calculation of the gate delay time the quasi-static approximation is assumed. The results confirm experimental data of carbon nanotube tr...

Field Programmable Gate Arrays (FPGAs) are frequently used to accelerate signal and image processing algorithms due to their flexibility, relatively low cost, high performance and fast time to market. For those applications where the data has large dynamic range, floating-point arithmetic is desirable due to the inherent limitations of fixed-point arithmetic. Moreover, optimal reconfigurable ha...

In this project we explore the capability and flexibility of FPGA solutions in a sense to accelerate scientific computing applications which require very high precision arithmetic, based on IEEE 754 standard 128-bit floating-point number representations. Field Programmable Gate Arrays (FPGA) is increasingly being used to design high end computationally intense microprocessors capable of handlin...