During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simulator. The cache simulator has been implemented using a retargetable instruction set simulator from the SimnML [9] processor description language. The retargetability helps in cache simulation and evaluation much before ...

In this paper, we present an investigation into the challenges in designing a network processor that is additionally capable of security processing. First, we provide an overview of the cryptographic algorithms utilized in security processing and highlight several current network protocols that employ these algorithms. Second, we discuss several issues in designing a solution for security proce...

Coarse-Grained Reconfigurable Architectures(CGRAs) can be employed for accelerating computational workloads that demand both flexibility and performance. CGRAs comprise a set of computation elements interconnected using a network and this interconnection of computation elements is referred to as a reconfigurable fabric. The size of application that can be accommodated on the reconfigurable fabr...

In recent years, dynamic reconfigurable processor which can achieve reconfiguration with a few cycles is proposed. The fast reconfiguration makes run-time reconfiguration possible, and the run-time reconfiguration gives a new possibility to the dynamic reconfigurable processor, i.e. the dynamic reconfigurable processor can also execute partitioned independent subtasks with repeated reconfigurat...

The Tera MTA (for \Multithreaded Architecture") computer features a radically new architecture, with hardware support for up to 128 threads per processor, a powerful instruction set, nearly uniform access time to all memory locations, and zero-cost synchronization and swapping between threads of control. Memory access latencies are tolerated by swapping between the threads. Given a multithreade...

Breaking out of the 1980s RISC mind set, Intel and Hewlett-Packard have designed a new instruction set, IA-64, geared toward the highly parallel processors of the next decade. IA-64 goes beyond previous CISC, RISC, and VLIW instruction sets with a new set of features that its creators call EPIC (explicitly parallel instruction computing). This strategy should give Merced, the first IA-64 chip, ...

(b) Approximation result We introduce a sequence of random variables yj with La = σ{yj; a ≤ j ≤ b}, and a sequence of integers 1 ≤M1 < M2 < M3 < · · · satisfying the following properties. Theorem 1.1 Let p < 2 ≤ 4. For any > 0, there exists Q,α > 0 and (a modified) τ ∈ (0, 1) such that In the Gibbs-Markov setting, we have the stronger mixing property |P (AB) − P (A)P (B)| ≤ CτP (A)P (B) 1 2 . I...

optimized asip synthesis from architecture description language models are a good way to achieve details about operating certainproducts. Many products that you buy can be obtained using instruction manuals. These user guides are clearlybuilt to give step-by-step information about how you ought to go ahead in operating certain equipments. Ahandbook is really a user's guide to operating the equi...

ÐThis paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, computation-intensive applications. MorphoSys is a coarse-grain, integrated, and reconfigurable system-on-chip, targeted at high-throughput and data-parallel applications. It is comprised of a reconfig...

The subject of this work is the design and the implementation of hardware components which can accelerate the computation in a microprocessor-based digital system controlled by a RISC (Reduced Instruction Set Computer) core. Indeed a RISC core alone cannot achieve the desired computational capability needed to meet the requirements of modern applications, especially demanding ones like audio/vi...