Digital circuit design is streamlined process used to improve the performance of a circuit for a particular application. Fast speed, minimum power dissipation and less area are the desirable characteristics of a digital circuit, in general. To meet a particular standard of speed, a compromise in power dissipation and speed is required. Timing elements such as Flip-flop are used as clock generat...

We present a framework that considers global routing, repeater insertion, and flip-flop relocation for early interconnect planning. We formulate the interconnect retiming and flip-flop placement problem as a local area constrained retiming problem and solve it as a series of weighted minimum area retiming problems. Our method for early interconnect planning can reduce and even avoid design iter...

Implementation of switching activity in the all-optical domain is an essential aspect modern high-speed and secured communication technology. Micro-ring Resonator (MRR) based can be used to implement active low tri-state buffer logic clocked D flip-flop. The paper describes micro-ring resonator structures. further effective 4-bit memory register using appropriate arrangement buffers flip-flops ...

Intrinsic Physical Unclonable Functions or PUFs have been introduced as a highly secure method to extract digital identifiers and keys from integrated circuits. In the setting of reconfigurable devices, like FPGAs, they can be used to protect the IP contained in the design in a cost-effective and tamper-evident way. In this work, a new type of PUF construction for reconfigurable devices is intr...

The fuzzy flip-flop based multilayer perceptron, named Fuzzy Neural Network, FNN is proposed for function approximation. In recent years much effort has been made for the development of a special kind of bacterial memetic algorithm for optimization and training of the fuzzy neural network parameters. In this approach the FNN parameters have been encoded in a chromosome and participate in the ba...

Equivalence checking tools often use a flip-flop matching step to avoid the state space traversal. Due to sequential optimizations performed during synthesis (merge, replication, redundancy removal, . . . ) and don’t care conditions, the matching step can be very complex as well as incomplete. If the matching is incomplete, even the use of a fast and efficient SAT solver during the combinationa...

of BDDbased 32-bit CRC encoder and decoder using LFSR methodology, with low power and less area. Generally 32-bit CRC is used in Ethernet frame for fault recognition at the transmitted data. The functional required for LFSR implementation is shift registers, flip flop which works for high frequency and yields less delay and consumes less power, the TSPC flip flop which is suitable for high spee...

Most biological membranes possess an asymmetric transbilayer distribution of phospholipids. Endogenous enzymes expend energy to maintain the arrangement by promoting the rate of phospholipid translocation, or flip-flop. Researchers have discovered ways to modify this distribution through the use of chemicals. This review presents a critical analysis of the phospholipid asymmetry data in the lit...

The two-gate bistable flip-flop may be generalised to a coupled structure of many gates having more stable states. These multi-flop structures have applications as arbiters to control mutually-exclusive access by several concurrent processes to a single service or resource. The paper illustrates some aspects of their complex dynamic behaviour.

Most important challenge in modern VLSI design along with area and speed is the power consumption. Flip flop is the basic element in digital system which plays very important role. In this paper, a low power pulse triggered flip flop with feed through technique is proposed. The proposed design introduces a series pass transistor which helps in reducing discharging path. By performing post layou...