The transcriptional repression of key regulatory genes is crucial for plant and animal development. Previously, we identified and isolated two Arabidopsis transcription co-repressors LEUNIG (LUG) and SEUSS (SEU) that function together in a putative co-repressor complex to prevent ectopic AGAMOUS (AG) transcription in flowers. Because neither LUG nor SEU possesses a recognizable DNA-binding moti...

Technology scaling relies on reduced nodal capacitances and lower voltages in order to improve performance and power consumption, resulting in significant increase in layout density, thus making these submicron technologies more susceptible to soft errors. Previous analysis indicates a significant improvement in SEU tolerance of the driver when the bias current is injected into the circuit but ...

This work is concerned with the vulnerability of spaceborne microelectronics to single event upset, a change of state caused by high-energy charged particles in the solar wind or the cosmic ray environment striking a sensitive node. To measure the susceptibility of a semiconductor device to single event upsets, testing is conducted by exposing it to highenergy heavy ions or protons produced in ...

Scientific Hardware/software techniques for the design of fault and malicious attacks resistant components and embedded systems Fields of expertise Test, Security, Self-Repair, Fault-tolerance : Methodologies, Tools and Architectures Know-how Multilevel platforms for fault simulation and robustness automatic insertion at several abstraction levels; 3D integration solutions test platform for rad...

The advent of reconfigurable hardware as a computing medium creates a multi-dimensional design space where trade-offs between power, speed, cost, and reliability are now possible. Dynamic reconfiguration allows these trade-offs to be made on-line to adapt to various environmental changes. Furthermore, the cost of designing reliable circuits is greatly reduced since varying levels of reliability...

At the system level, SEUs in processors are controlled by fault-tolerance techniques such as replication and voting, watchdog processors, and tagged data schemes [13,16,30]. SEUs in memory subsystems are controlled by use of error control codes (ECCs) [4,17,21] and a process called scrubbing. The scrubbing process periodically reads each word in the memory. If the number of faulty digits in a w...

Recently, the soft error rates of integrated circuits is increased by process scaling. Soft error decreases the tolerance of VLSIs. Charge sharing and bipolar effect become dominant when a particle hit on latches and flip-flop. soft error makes circuit more sensitive to Multiple Cell Upset (MCU). We analyze the MCU tolerance of redundant latches in 65 nm process by device simulation and particl...

Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loops of the implemented circuits. In this paper, we a) provide a netlist-based circuit analysis technique to distinguish so-called critical configuration bits from essential bits in order to identify configuration bits ...

We measured neutron-induced SEUs (Single Event Upsets) and MCUs (Multiple Cell Upsets) on FFs in a 65 nm bulk CMOS process. Measurement results show that maximum MCU / SEU ratio is 30.6% and is exponentially decreased by the distance between latches on FFs.

By inducing two-photon absorption within the active layer of a 28nm test chip, we demonstrate nonlinear laser-assisted device alteration and single-event upsets by temporarily perturbing the timing characteristics of sensitive transistors. Individual qualitative and quantitative evaluations are presented for both techniques, with lateral resolutions demonstrated with sub-100nm performance. A si...