Increased lower metal resistance makes physical aspects of Field-Programmable Gate Array (FPGA) switch-blocks more relevant than before. The need to navigate a design space where each individual switch can have significant impact on the FPGA’s performance in turn automated switch-pattern exploration techniques increasingly appealing. However, most existing fundamental limitation—they use CAD to...

The main emphasis in developing DOS has been on achieving low crosstalk (CT). CT in the order of -30 dB is acceptable in conventional DOS and below that value is hard to achieve. Relatively low drive voltage (or power requirements) is also necessary to optimized DOS. This paper depicts the design of Y-branched digital optical switches (DOS) with optimized on-chip area coverage, reduced driving ...

This study proposes a novel Three-Dimensional Virtual Output Queue (3D-VOQ) switch architecture to emulate an output-queued switch operating only at the line speed. The 3D-VOQ switch needs no speedup, and emulates an output-queued switch precisely with a broad class of service scheduling algorithms irrespective of its incoming traffic pattern and switch size. An N×N 3D-VOQ switch is first propo...

This letter proposes a combined inputand crosspoint-queued (CIC) switch in which virtual output queuing (VOQ) is used at each input port. This CIC switch has a large buffer at each input port and a small buffer at each crosspoint. It does not require high-speed memory access or high-speed internal cell transmission lines. Since the performance of the CIC switch depends on the scheduling algorit...

in this paper, a new topology is proposed for three-phase to single-phase matrix converters, where more voltage levels are produced in the output in comparison with the conventional topologies. in addition, a new control method based on minimum error between the generated and the desired output voltages is proposed for three-phase to single-phase matrix converters. in the proposed control metho...