This paper presents a novel algorithm and architecture for digital frequency synthesis DFS . It is based on a simple difference equation. Simulation results show that the proposed DFS algorithm is preferable to the conventional phase-locked-loop frequency synthesizer and the direct digital frequency synthesizer in terms of the spurious-free dynamic range SFDR and the peak-signalto-noise ratio P...

a 0.4-pm digit l CMOS technology entails many difficulties This paper describes the design of a CMOS frequency synthesizer targeting wireless local area network applications in the 5-GHz range. Based on an integer-N architecture, the synthesizer produces a 5.2-GHz output as well as the quadrature phases of a 2.6-GHz carrier. Fabricated in a 0.4-pm digital CMOS technology, the circuit provides a...

The quality of the vocoder plays a crucial role in the performance of parametric speech synthesis systems. In order to improve the vocoder quality, it is necessary to reconstruct as much of the perceived components of the speech signal as possible. In this paper, we first show that the noise component is currently not accurately modelled in the widely used STRAIGHT vocoder, thus, limiting the v...

In this paper, we propose an all-digital frequency output of the synthesizer. High reference frequency (REF) is synthesizer architecture, based on an all-digital XA-frequency used to push the spurs far from the carrier. The need for high discriminator. The new all-digital synthesizer is compared to sampling frequency, in addition to the resolution being previously published work. The architectu...

This paper presents a Wireless-USB/WiMedia-compliant fast-hopping frequency synthesizer architecture with quadrature outputs based on sub-harmonic injection-locking. The synthesizer features a cross-coupled quadrature digitally-controlled oscillator, that is injection-locked to a sub-harmonic frequency. An intuitive closed-form expression for the dynamics of the quadrature injection-locked osci...