An all-digital fractional-N Phase-Locked Loop (PLL) built with standard cells and digital synthesis tools allows easier integration with digital blocks and portability to different processes or technologies. This paper presents a PLL built with standard cells and digital synthesis tools and achieves good jitter performance. It uses an embedded time-to-digital converter (TDC) with multipath to i...

An 80MS/s analog-to-digital converter (ADC) based on single-slope conversion is presented which utilizes a recently developed gated ring oscillator (GRO) time-to-digital converter (TDC) to achieve an ENOB of 6.45 bits. To save power, the time-to-digital conversion is done in two steps, the first of which is based on coarse time quantization as measured by cycles of an oscillator and the second ...

This paper presents an integrated receiver channel and an integrated time-to-digital (TDC) converter fabricated in a 0.35 mm SiGe BiCMOS and in 0.35 mm CMOS technologies, respectively, that give the required performance for a pulsed time-of-flight (TOF) laser radar to be used in a laser scanner in automotive applications. The receiver-TDC chip set is capable to measure the positions and widths ...

Immunization of mice with peptide constructs, consisting of a determinant recognized by T cytotoxic cells colinearly linked to a determinant recognized by T helper cells (TDc-TDh) was able to induce cytotoxic T lymphocytes in vivo. Interestingly, this induction could be achieved in the absence of adjuvant in non-depleted as well as in CD4(+)-cell-depleted BALB/c mice. In the latter case, induct...

We propose a time-to-digital converter (TDC) using a charge pump and a SAR-ADC. With this architecture, high time resolution is attainable by increasing the charging current or reducing the sampling capacitance. Thus, the resolution limitation in a delay-chain TDC does not exist. We propose to use a SAR-ADC attributed to its characteristics of compact structure, scalability, low power consumpti...

This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. T...

the rapid scaling in modern cmos technology has motivated the researchers to design new analog-to-digital converter (adc) architectures that can properly work in lower supply voltage. an exchanging the data quantization procedure from the amplitude to the time domain, can be a promising alternative well adapt with the technology scaling. this paper is going to review the recent development in t...

This paper proposes a low-power all-digital phase-locked loop (ADPLL) with calibration-free ring oscillator (RO)-based injection-locking time to digital converter (TDC) for BLE applications. The RO is reused as the delay cell of TDC, and quantization step TDC always tracked period; hence no calibration needed in this architecture. We adopt tuning lower bandwidth so decrease power consumption in...

Ao ingressarem na universidade, estudantes entram em contato com diversos gêneros e atividades que requerem diferentes tipos de letramentos. Na área da biologia, uma delas refere-se à leitura textos divulgação científica (TDC) língua inglesa. Assim, ofertamos oficina a do primeiro ano curso Ciências Biológicas UEL abordando esta atividade. Fundamentado estudos sobre o gênero TDC rubricas, este ...

Navitoclax (ABT-263), a Bcl-2 family inhibitor and ABT-199, a Bcl-2 selective inhibitor, are high molecular weight, high logP molecules that show low solubility in aqueous media. While these properties are associated with low oral bioavailability (F), both navitoclax and ABT-199 showed moderate F in preclinical species. The objective of the described study was to determine if lymphatic transpor...