A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the design of this basic adder unit. The speed of operation of a circuit is one of the important performance criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many research works have been devoted in improving the delay of the adder circuit. In t...

In this paper, various designs of low-power full-adder cell are studied. Simulation of these full-adder cells are carried out. The experiments simulate all combinations of input transitions and consequently determine the power consumption for the various full-adder cells. The simulation results highlight the weaknesses and the strengths of the various full-adder cell designs. The high performan...

In this paper, a full adder cell based on majority function using Carbon-Nanotube Field-Effect Transistor (CNFET) technology is presented. CNFETs possess considerable features that lead to their wide usage in digital circuits design. For the design of the cell input capacitors and inverters are used. These kinds of design method cause a high degree of regularity and simplicity. The proposed des...

This paper presents the design and implementation of a time driven adder generator architecture. There exists a large variety of adders designed to satisfy different computation requirements, in particular we list the Carry Look Ahead (CLA) adder, the skip adder, the ripple adder, the carry select adder (CSA), etc. These different architectures will offer different delays and it is up to the us...

We present the basic structure and performance of CML current mode full adders, that are used as Carry Save Adders (CSA) in combinatorial multipliers. A 1.2 μm BiCMOS technology is used for simulations but the schematic assumes a 2.5-V power supply. Compared with binary voltage mode CSAs, the multivalued current mode CSAs have chip area and power dissipation advantage, but speed disadvantage. T...

Micro-electronic devices are playing a very prominent role in electronic equipments which are used in daily life. For electronic equipment battery life is important. So, in order to reduce the power consumption we implement a Sleepy technique to the electronic circuits. Sleepy technique is also called as power gating technique. In the power gating structure, a circuit operates in two different ...

In this paper we propose a modified probabilistic estimation bias (PEB) formula for fixed-width radix-4 Booth multiplier. The modified PEB formula estimates the same compensation value as the existing PEB formula without rounding operation. A bias circuit based on modified PEB formula generates one less carry-bit and involves less logic resources than the existing PEB circuit. The partial produ...

the full adders (fas) constitute the essential elements of digital systems, in a sense that they affect the circuit parameters of such systems. with respect to the mosfet restrictions, its replacement by new devices and technologies is inevitable. qca is one of the accomplishments in nanotechnology nominated as the candidate for mosfet replacement. in this article 4 new layouts are presented fo...