design space exploration, VLIW, systolic array, cache This paper addresses the problem of automated design of a computer system for an embedded application. The computer system to be designed consists of a VLIW processor and/or a customized systolic array, along with a cache subsystem comprising a data cache, instruction cache and second-level unified cache. Several algorithms for "walking" the...

Software-Based Self-Test (SBST) approaches have shown to be an effective solution to detect permanent faults, both at the end of the production process, and during the operational phase. However, when Very Long Instruction Word (VLIW) processors are addressed these techniques require some optimization steps in order to properly exploit the parallelism intrinsic in these architectures. In this c...

instruction-level parallelism, VLIW processors, superscalar processors, pipelining, multiple operation issue, scoreboarding, dynamic scheduling, out-of -order execution VLIW processors are viewed as an attractive way of achieving instruction-level parallelism because of their ability to issue multiple operations per cycle with relatively simple control logic. They are also perceived as being of...

This paper describes the mapping of Finite Impulse Response (FIR) and Decimation filters on a new DSP architecture: the Co-Vector Processor (CVP) developed by Philips. This architecture is targeting the baseband signal processing algorithms for the third generation mobile communication (3G). CVP is a Very Long Instruction Word (VLIW) architecture with functional units supporting vector parallel...

This study compares the speed, area, and power of diier-ent implementations of Active Pages OCS98], an intelligent memory system which helps bridge the growing gap between processor and memory performance by associating simple functions with each page of data. Previous investigations have shown up to 1000X speedups using a block of reconng-urable logic to implement these functions next to each ...

This dissertation explores high-performance complexity-efficient processors focusing on VLIW processors. Complexity efficiency is a qualitative characteristic that describes a system where performance has not reached the point of diminishing returns. Using the techniques described in this dissertation, simple statically-scheduled very-long-instructionword (VLIW) processors can be efficient arch...

We describe full system simulation of DAISY (Dynamically Architected Instruction Set from Yorktown). At runtime DAISY dynamically translates code for a PowerPC processor into code for an underlying VLIW processor. Our style of simulation can also be used in the context of full system emulation à la SimOS and SimICS. Unlike SimOS and SimICS, DAISY emulation is operating system and device indepen...

HAVANKI, WILLIAM ANDREW, JR. Treegion Scheduling for VLIW Processors. (Under the direction of Dr. Thomas M. Conte.) The instruction scheduling phase of compilation is an important determinant of VLIW program performance. One scheduling framework divides a program into regions of code that tend to execute together, and then constructs schedules for each region. Several regions suggested in the p...

This paper aims to provide a quantitative understanding of the performance of DSP and multimedia applications on very long instruction word (VLIW), single instruction multiple data (SIMD), and superscalar processors. We evaluate the performance of the VLIW paradigm using Texas Instruments Inc.’s TMS320C62xx processor and the SIMD paradigm using Intel’s Pentium II processor (with MMX) on a set o...

We propose a low-power resource-shared VLIW processor (RSVP) for future leaky nanometer process technologies. It consists of several single-way independent processor units (IPUs) that share parallel processor resources. Each IPU works as a variable-way VLIW processor sharing the parallel resources according to priorities of given tasks. RSVP allocates shared parallel resources to the IPUs cycle...